Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 465 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
Vector table — If the program changes an entry in the vector table, and then enables the
corresponding exception, use a
DMB instruction between the operations. This ensures that
if the exception is taken immediately after being enabled the processor uses the new
exception vector.
Self-modifying code — If a program contains self-modifying code, use an
ISB instruction
immediately after the code modification in the program. This ensures subsequent
instruction execution uses the updated program.
Memory map switching — If the system contains a memory map switching mechanism,
use a
DSB instruction after switching the memory map. This ensures subsequent
instruction execution uses the updated memory map.
Memory accesses to Strongly-ordered memory, such as the System Control Block, do not
require the use of
DMB instructions.
The processor preserves transaction order relative to all other transactions.
28.4.2.5 Memory endianness
The processor views memory as a linear collection of bytes numbered in ascending order
from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the
second stored word. Section 28–28.4.2.5.1
describes how words of data are stored in
memory.
28.4.2.5.1 Little-endian format
In little-endian format, the processor stores the least significant byte (lsbyte) of a word at
the lowest-numbered byte, and the most significant byte (msbyte) at the
highest-numbered byte. For example:
28.4.3 Exception model
This section describes the exception model.
28.4.3.1 Exception states
Each exception is in one of the following states:
Inactive — The exception is not active and not pending.
Pending — The exception is waiting to be serviced by the processor.
Fig 100. Little-endian format
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