Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 497 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
28.5.6.1 B, BL, BX, and BLX
Branch instructions.
28.5.6.1.1 Syntax
B{cond} label
BL label
BX Rm
BLX Rm
where:
cond is an optional condition code, see Section 28–28.5.3.6
.
label is a PC-relative expression. See Section 28–28.5.3.5
.
Rm is a register providing the address to branch to.
28.5.6.1.2 Operation
All these instructions cause a branch to the address indicated by label or contained in the
register specified by Rm. In addition:
• The BL and BLX instructions write the address of the next instruction to LR, the link
register R14.
• The BX and BLX instructions result in a HardFault exception if bit[0] of Rm is 0.
BL and BLX instructions also set bit[0] of the LR to 1. This ensures that the value is
suitable for use by a subsequent POP {PC} or BX instruction to perform a successful
return branch.
Table 438
shows the ranges for the various branch instructions.
28.5.6.1.3 Restrictions
In these instructions:
• Do not use SP or PC in the BX or BLX instruction.
BL Branch with Link Section 28–28.5.6.1
BLX Branch indirect with Link Section 28–28.5.6.1
BX Branch indirect Section 28–28.5.6.1
Table 437. Branch and control instructions
Mnemonic Brief description See
Table 438. Branch ranges
Instruction Branch range
B label 2 KB to +2 KB
Bcond label 256 bytes to +254 bytes
BL label 16 MB to +16 MB
BX Rm Any value in register
BLX Rm Any value in register