Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 502 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
28.5.7.6.4 Condition flags
This instruction does not change the flags.
28.5.7.6.5 Examples
MRS R0, PRIMASK ; Read PRIMASK value and write it to R0
28.5.7.7 MSR
Move the contents of a general-purpose register into the specified special register.
28.5.7.7.1 Syntax
MSR spec_reg, Rn
where:
Rn is the general-purpose source register.
spec_reg is the special-purpose destination register: APSR, IPSR, EPSR, IEPSR,
IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, or CONTROL.
28.5.7.7.2 Operation
MSR updates one of the special registers with the value from the register specified by Rn.
See Section 28–28.5.7.6
.
28.5.7.7.3 Restrictions
In this instruction, Rn must not be SP and must not be PC.
28.5.7.7.4 Condition flags
This instruction updates the flags explicitly based on the value in Rn.
28.5.7.7.5 Examples
MSR CONTROL, R1 ; Read R1 value and write it to the CONTROL register
28.5.7.8 NOP
No Operation.
28.5.7.8.1 Syntax
NOP
28.5.7.8.2 Operation
NOP performs no operation and is not guaranteed to be time consuming. The processor
might remove it from the pipeline before it reaches the execution stage.
Use NOP for padding, for example to place the subsequent instructions on a 64-bit
boundary.
28.5.7.8.3 Restrictions
There are no restrictions.