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ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller HVQFN 32 (7x7) 32-Bit 50 MHz I/O number 28

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User manual Rev. 12.3 — 10 June 2014 510 of 547

NXP Semiconductors

UM10398

Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference

– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this

is pulsed the state of the interrupt changes to pending and active. In this case,

when the processor returns from the ISR the state of the interrupt changes to

pending, which might cause the processor to immediately re-enter the ISR.

If the interrupt signal is not pulsed while the processor is in the ISR, when the

processor returns from the ISR the state of the interrupt changes to inactive.

• Software writes to the corresponding interrupt clear-pending register bit.

For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the

interrupt does not change. Otherwise, the state of the interrupt changes to inactive.

For a pulse interrupt, state of the interrupt changes to:

– inactive, if the state was pending

– active, if the state was active and pending.

28.6.2.8 NVIC usage hints and tips

Ensure software uses correctly aligned register accesses. The processor does not

support unaligned accesses to NVIC registers.

An interrupt can enter pending state even if it is disabled. Disabling an interrupt only

prevents the processor from taking that interrupt.

28.6.2.8.1 NVIC programming hints

Software uses the

CPSIE i

and CPSID i instructions to enable and disable interrupts. The

CMSIS provides the following intrinsic functions for these instructions:

void __disable_irq(void) // Disable Interrupts

void __enable_irq(void) // Enable Interrupts

In addition, the CMSIS provides a number of functions for NVIC control, including:

The input parameter IRQn is the IRQ number, see Table 28–428 for more information. For

more information about these functions, see the CMSIS documentation.

28.6.3 System Control Block

The System Control Block (SCB) provides system implementation information, and

system control. This includes configuration, control, and reporting of the system

exceptions. The SCB registers are:

Table 448. CMSIS functions for NVIC control

CMSIS interrupt control function Description

void NVIC_EnableIRQ(IRQn_t IRQn)

Enable IRQn

void NVIC_DisableIRQ(IRQn_t IRQn)

Disable IRQn

uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn)

Return true (1) if IRQn is pending

void NVIC_SetPendingIRQ (IRQn_t IRQn)

Set IRQn pending

void NVIC_ClearPendingIRQ (IRQn_t IRQn)

Clear IRQn pending status

void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority)

Set priority for IRQn

uint32_t NVIC_GetPriority (IRQn_t IRQn)

Read priority of IRQn

void NVIC_SystemReset (void)

Reset the system