Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 513 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
[1] This is the same value as IPSR bits[5:0], see Table 28–423.
[2] See Section 28.1
for implementation of the NMI for specific parts.
When you write to the ICSR, the effect is Unpredictable if you:
• write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit
• write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit.
28.6.3.4 Application Interrupt and Reset Control Register
The AIRCR provides endian status for data accesses and reset control of the system. See
the register summary in Table 28–449
and Table 28–452 for its attributes.
To write to this register, you must write
0x05FA to the VECTKEY field, otherwise the
processor ignores the write.
The bit assignments are:
[25] PENDSTCLR WO SysTick exception clear-pending bit.
Write:
0 = no effect
1 = removes the pending state from the SysTick
exception.
This bit is WO. On a register read its value is Unknown.
[24:23] - - Reserved.
[22] ISRPENDING RO Interrupt pending flag, excluding NMI and Faults:
0 = interrupt not pending
1 = interrupt pending.
[21:18] - - Reserved.
[17:12] VECTPENDING RO Indicates the exception number of the highest priority
pending enabled exception:
0 = no pending exceptions
Nonzero = the exception number of the highest priority
pending enabled exception.
[11:6] - - Reserved.
[5:0] VECTACTIVE
[1]
RO Contains the active exception number:
0 = Thread mode
Nonzero = The exception number
[1]
of the currently
active exception.
Remark: Subtract 16 from this value to obtain the
CMSIS IRQ number that identifies the corresponding bit
in the Interrupt Clear-Enable, Set-Enable,
Clear-Pending, Set-pending, and Priority Register, see
Table 28–423
.
Table 451. ICSR bit assignments
Bits Name Type Function