Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 516 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
28.6.3.7.2 System Handler Priority Register 3
The bit assignments are:
28.6.3.8 SCB usage hints and tips
Ensure software uses aligned 32-bit word size transactions to access all the SCB
registers.
28.6.4 System timer, SysTick
When enabled, the timer counts down from the current value (SYST_CVR) to zero,
reloads (wraps) to the value in the SysTick Reload Value Register (SYST_RVR) on the
next clock edge, then decrements on subsequent clocks. When the counter transitions to
zero, the COUNTFLAG status bit is set to 1. The COUNTFLAG bit clears on reads.
Remark: The SYST_CVR value is UNKNOWN on reset. Software should write to the
register to clear it to zero before enabling the feature. This ensures the timer will count
from the SYST_RVR value rather than an arbitrary value when it is enabled.
Remark: If the SYST_RVR is zero, the timer will be maintained with a current value of
zero after it is reloaded with this value. This mechanism can be used to disable the feature
independently from the timer enable bit.
A write to the SYST_CVR will clear the register and the COUNTFLAG status bit. The write
causes the SYST_CVR to reload from the SYST_RVR on the next timer clock, however, it
does not trigger the SysTick exception logic. On a read, the current value is the value of
the register at the time the register is accessed.
Remark: When the processor is halted for debugging the counter does not decrement.
The system timer registers are:
[1] SysTick calibration value.
Table 456. SHPR2 register bit assignments
Bits Name Function
[31:24] PRI_11 Priority of system handler 11, SVCall
[23:0] - Reserved
Table 457. SHPR3 register bit assignments
Bits Name Function
[31:24] PRI_15 Priority of system handler 15, SysTick exception
[23:16] PRI_14 Priority of system handler 14, PendSV
[15:0] - Reserved
Table 458. System timer registers summary
Address Name Type Reset
value
Description
0xE000E010 SYST_CSR RW 0x00000000 Section 28.6.4.1
0xE000E014 SYST_RVR RW Unknown Section 28–28.6.4.2
0xE000E018 SYST_CVR RW Unknown Section 28–28.6.4.3
0xE000E01C SYST_CALIB RO 0x00000004
[1]
Section 28–28.6.4.4