Datasheet

LPC11U6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1.2 — 26 May 2014 32 of 96
NXP Semiconductors
LPC11U6x
32-bit ARM Cortex-M0+ microcontroller
8.19.1.1 Features
Each SCTimer/PWM supports:
5 match/capture registers.
6 events.
8 states.
4 inputs and 4 outputs.
Counter/timer features:
Each SCTimer is configurable as two 16-bit counters or one 32-bit counter.
Counters can be clocked by the system clock or selected input.
Configurable as up counters or up-down counters.
Configurable number of match and capture registers. Up to five match and capture
registers total.
Upon match create the following events: interrupt; stop, limit, halt the timer or
change counting direction; toggle outputs.
Counter value can be loaded into capture register triggered by a match or
input/output toggle.
PWM features:
Counters can be used with match registers to toggle outputs and create
time-proportioned PWM signals.
Up to four single-edge or dual-edge PWM outputs with independent duty cycle and
common PWM cycle length.
Event creation features:
The following conditions define an event: a counter match condition, an input (or
output) condition such as a rising or falling edge or level, a combination of match
and/or input/output condition.
Selected events can limit, halt, start, or stop a counter or change its direction.
Events trigger state changes, output toggles, interrupts, and DMA transactions.
Match register 0 can be used as an automatic limit.
In bidirectional mode, events can be enabled based on the count direction.
Match events can be held until another qualifying event occurs.
State control features:
A state is defined by events that can happen in the state while the counter is
running.
A state changes into another state as a result of an event.
Each event can be assigned to one or more states.
State variable allows sequencing across multiple counter cycles.
SCTimer match outputs (ORed with the general-purpose timer match outputs) serve
as ADC hardware trigger inputs.