Datasheet

LPC11U6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1.2 — 26 May 2014 33 of 96
NXP Semiconductors
LPC11U6x
32-bit ARM Cortex-M0+ microcontroller
8.19.2 General purpose external event counter/timers (CT32B0/1 and CT16B0/1)
The LPC11U6x includes two 32-bit counter/timers and two 16-bit counter/timers. The
counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes one capture input to trap the timer value
when an input signal transitions, optionally generating an interrupt.
8.19.2.1 Features
• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
• Counter or timer operation.
• One capture channel per timer, that can take a snapshot of the timer value when an
input signal transitions. A capture event may also generate an interrupt.
• Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• The timer and prescaler may be configured to be cleared on a designated capture
event. This feature permits easy pulse-width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
• PWM output function.
• Match outputs and capture inputs serve as hardware triggers for ADC conversions.
8.20 System tick timer (SysTick)
The ARM Cortex-M0+ includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
8.21 Windowed WatchDog Timer (WWDT)
The purpose of the WWDT is to prevent an unresponsive system state. If software fails to
update the watchdog within a programmable time window, the watchdog resets the
microcontroller
8.21.1 Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.