Datasheet

Product data sheet Rev. 1.2 — 26 May 2014 38 of 96

NXP Semiconductors

LPC11U6x

32-bit ARM Cortex-M0+ microcontroller

8.25.3.1 Internal RC oscillator

The IRC can be used as the clock source for the WDT, the USB PLL in low-speed USB

applications, or as the clock that drives the system PLL and then the CPU. The nominal

IRC frequency is 12 MHz.

Upon power-up, any chip reset, or wake-up from Deep power-down mode, the LPC11U6x

use the IRC as the clock source. Software can later switch to one of the other available

clock sources.

8.25.3.2 System oscillator

The system oscillator can be used as the clock source for the CPU, with or without using

the PLL. Use the system oscillator to provide the clock source to USB.

The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be

boosted to a higher frequency, up to the maximum CPU operating frequency, by the

system PLL.

The system oscillator has a wake-up time of approximately 500 s.

8.25.3.3 WatchDog oscillator

The watchdog oscillator can be used as a clock source that directly drives the CPU, the

watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is

programmable between 9.4 kHz and 2.3 MHz. The frequency spread over processing and

temperature is 40 % (see also Table 14

8.25.3.4 RTC oscillator

The low-power RTC oscillator provides a 1 Hz clock and a 1 kHz clock to the RTC and a

32 kHz clock output that can be used to obtain the main clock (see Figure 10

8.25.4 System PLL and USB PLL

The LPC11U6x contain a system PLL and a dedicated PLL for generating the 48 MHz

USB clock. The system and USB PLLs are identical.

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz. To support this frequency range, an additional divider keeps the

CCO within its frequency range while the PLL is providing the desired output frequency.

The output divider can be set to divide by 2, 4, 8, or 16 to produce the output clock. The

PLL output frequency must be lower than 100 MHz. Since the minimum output divider

value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off

and bypassed following a chip reset. Software can enable the PLL later. The program

must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL

as a clock source. The PLL settling time is 100 s.

8.25.5 Clock output

The LPC11U6x feature a clock output function that routes the IRC oscillator, the system

oscillator, the watchdog oscillator, or the main clock to an output pin.