Datasheet

Product data sheet Rev. 1.2 — 26 May 2014 41 of 96

NXP Semiconductors

LPC11U6x

32-bit ARM Cortex-M0+ microcontroller

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values. The internal reset

status is reflected on the RSTOUT

pin.

In Deep power-down mode, an external pull-up resistor is required on the RESET

pin.

The RESET

pin is operational in active, sleep, deep-sleep, and power-down modes if the

RESET

function is selected in the IOCON register for pin PIO0_0 (this is the default). A

LOW-going pulse as short as 50 ns executes the reset and also wakes up the part if in

sleep, deep-sleep or power-down mode. The RESET

pin is not functional in Deep

power-down mode.

8.26.2 Brownout detection

The LPC11U6x includes two levels for monitoring the voltage on the V

pin. If this

voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the

NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC

to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a

dedicated status register. Two threshold levels can be selected to cause a forced reset of

the chip.

8.26.3 Code security (Code Read Protection - CRP)

CRP provides different levels of security in the system so that access to the on-chip flash

and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be

restricted. Programming a specific pattern into a dedicated flash location invokes CRP.

IAP commands are not affected by the CRP.

In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For

details, see the LPC11Uxx user manual.

There are three levels of Code Read Protection:

Fig 12. RESET pin configuration

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