Datasheet

Product data sheet Rev. 3 — 20 September 2012 35 of 77

NXP Semiconductors

LPC1315/16/17/45/46/47

32-bit ARM Cortex-M3 microcontroller

7.18.5.4 Power-down mode

In Power-down mode, the LPC1315/16/17/45/46/47 is in Sleep-mode and all peripheral

clocks and all clock sources are off with the exception of watchdog oscillator if selected. In

addition all analog blocks and the flash are shut down. In Power-down mode, the user has

the option to keep the BOD circuit running for BOD protection.

The LPC1315/16/17/45/46/47 can wake up from Power-down mode via reset, selected

GPIO pins, a watchdog timer interrupt, or an interrupt generating USB port activity.

Power-down mode reduces power consumption compared to Deep-sleep mode at the

expense of longer wake-up times.

7.18.5.5 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip with the exception of the

WAKEUP pin. The LPC1315/16/17/45/46/47 can wake up from Deep power-down mode

via the WAKEUP pin.

The LPC1315/16/17/45/46/47 can be prevented from entering Deep power-down mode by

setting a lock bit in the PMU block. Locking out Deep power-down mode enables the user

to always keep the watchdog timer or the BOD running.

When entering Deep power-down mode, an external pull-up resistor is required on the

WAKEUP pin to hold it HIGH. The RESET

pin must also be held HIGH to prevent it from

floating while in Deep power-down mode.

7.18.6 System control

7.18.6.1 Reset

Reset has four sources on the LPC1315/16/17/45/46/47: the RESET

pin, the Watchdog

reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET

is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating

voltage attains a usable level, starts the IRC and initializes the flash controller.

A LOW-going pulse as short as 50 ns resets the part.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

An external pull-up resistor is required on the RESET

pin if Deep power-down mode is

used.

7.18.6.2 Brownout detection

The LPC1315/16/17/45/46/47 includes up to four levels for monitoring the voltage on the

pin. If this voltage falls below one of selected levels, the BOD asserts an interrupt

signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable

signal by reading a dedicated status register. Four threshold levels can be selected to

cause a forced reset of the chip.