Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 80 (12x12) 32-Bit 120 MHz I/O number 52

1. General description

The LPC1759/58/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded

applications featuring a high level of integration and low power consumption. The ARM

Cortex-M3 is a next generation core that offers system enhancements such as enhanced

debug features and a higher level of support block integration.

The LPC1758/56/57/54/52/51 operate at CPU frequencies of up to 100 MHz. The

LPC1759 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU

incorporates a 3-stage pipeline and uses a Harvard architecture with separate local

instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3

CPU also includes an internal prefetch unit that supports speculative branching.

The peripheral complement of the LPC1759/58/56/54/52/51 includes up to 512 kB of flash

memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface,

8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers,

SPI interface, 2 I

C-bus interfaces, 2-input plus 2-output I

S-bus interface, 6 channel

12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, 4 general

purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC)

with separate battery supply, and up to 52 general purpose I/O pins.

For additional documentation, see Section 19 “

References”.

2. Features and benefits

 ARM Cortex-M3 processor, running at frequencies of up to 100 MHz

(LPC1758/56/57/54/52/51) or of up to 120 MHz (LPC1759). A Memory Protection Unit

(MPU) supporting eight regions is included.

 ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

 Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator

enables high-speed 120 MHz operation with zero wait states.

 In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.

 On-chip SRAM includes:

 Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance

CPU access.

 Two/one 16 kB SRAM blocks with separate access paths for higher throughput.

These SRAM blocks may be used for Ethernet (LPC1758 only), USB, and DMA

memory, as well as for general purpose CPU instruction and data storage.

LPC1759/58/56/54/52/51

32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB

SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN

Rev. 8.5 — 24 June 2014 Product data sheet

Summary of content (80 pages)

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LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN Rev. 8.5 — 24 June 2014 Product data sheet 1. General description The LPC1759/58/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.
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NXP Semiconductors LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller  Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S-bus, UART, the Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.  Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller                    WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.  ARM Cortex-M3 system tick timer, including an external clock input option.  Repetitive Interrupt Timer (RIT) provides programmable and repeating timed interrupts.  Each peripheral has its own clock divider for further power savings.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC1759FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12  12  1.4 mm SOT315-1 LPC1758FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12  12  1.4 mm SOT315-1 LPC1756FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12  12  1.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 5. Marking The LPC175x devices typically have the following top-side marking: LPC175xxxx xxxxxxx xxYYWWR[x] The last/second to last letter in the third line (field ‘R’) will identify the device revision. This data sheet covers the following revisions of the LPC175x: Table 3.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 6.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7. Pinning information 40 80 21 20 61 1 Fig 2. 41 60 7.1 Pinning 002aae158 Pin configuration LQFP80 package 7.2 Pin description Table 4.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4. Pin description …continued Symbol Pin Type Description P0[7]/I2STX_CLK/ SCK1/MAT2[1] 63[1] I/O P0[7] — General purpose digital input/output pin. I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1759/58/56 only). I/O SCK1 — Serial Clock for SSP1. O MAT2[1] — Match output for Timer 2, channel 1.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4. Pin description …continued Symbol Pin Type Description P0[22]/RTS1/TD1 44[1] I/O P0[22] — General purpose digital input/output pin. O RTS1 — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. O TD1 — CAN1 transmitter output. I/O P0[25] — General purpose digital input/output pin. I AD0[2] — A/D converter 0, input 2. I/O I2SRX_SDA — Receive data.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4. Pin description …continued Symbol Pin Type Description P1[18]/ USB_UP_LED/ PWM1[1]/ CAP1[0] 25[1] I/O P1[18] — General purpose digital input/output pin. O USB_UP_LED — USB GoodLink LED indicator. It is LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4. Pin description …continued Symbol Pin Type Description P1[28]/MCOA2/ PCAP1[0]/ MAT0[0] 35[1] I/O P1[28] — General purpose digital input/output pin. O MCOA2 — Motor control PWM channel 2, output A. I PCAP1[0] — Capture input for PWM1, channel 0. O MAT0[0] — Match output for Timer 0, channel 0. P1[29]/MCOB2/ PCAP1[1]/ MAT0[1] 36[1] I/O P1[29] — General purpose digital input/output pin.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4. Pin description …continued Symbol Pin Type Description P2[6]/PCAP1[0]/ RI1/TRACECLK 52[1] I/O P2[6] — General purpose digital input/output pin. I PCAP1[0] — Capture input for PWM1, channel 0. I RI1 — Ring Indicator input for UART1. O TRACECLK — Trace Clock. I/O P2[7] — General purpose digital input/output pin. I RD2 — CAN2 receiver input. (LPC1759/58/56 only).
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4. Pin description …continued Symbol Pin Type Description XTAL1 19[9][10] I Input to the oscillator circuit and internal clock generator circuits. XTAL2 20[9][10] O Output from the oscillator amplifier. RTCX1 13[9][11] I Input to the RTC oscillator circuit. RTCX2 15[9] O Output from the RTC oscillator circuit. VSS 24, 33, 43, 57, 66, 78 I ground: 0 V reference.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8. Functional description 8.1 Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the system bus and are used similarly to Tightly Coupled Memory (TCM) interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code).
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.5 Memory Protection Unit (MPU) The LPC1759/58/56/54/52/51 have a Memory Protection Unit (MPU) which can be used to improve the reliability of an embedded system by protecting critical data within the user application.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.7 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 8.7.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.9.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode. 8.10.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Cyclic Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision back-off and frame retransmission.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • While USB is in the Suspend mode, the LPC1759/58/56/54/52/51 can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints. • Allows dynamic switching between CPU-controlled slave and DMA modes. • Double buffer implementation for Bulk and Isochronous endpoints. 8.12.2 USB host controller (LPC1759/58/56/54 only).
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.13.1 Features • • • • • One or two CAN controllers and buses. Data rates to 1 Mbit/s on each bus. 32-bit register and RAM access. Compatible with CAN specification 2.0B, ISO 11898-1. Global Acceptance Filter recognizes standard (11-bit) and extended-frame (29-bit) receive identifiers for all CAN buses. • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.16 UARTs The LPC1759/58/56/54/52/51 each contain four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. The UARTs include a fractional baud rate generator.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 8.18.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S connection has one master, which is always the master, and one slave. The I2S-bus interface provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 8.20.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller – Do nothing on match. • Up to two match registers can be used to generate timed DMA requests. 8.22 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC1759/58/56/54/52/51.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.25 Repetitive Interrupt (RI) timer The repetitive interrupt timer provides a free-running 32-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare can be masked such that they do not contribute to the match detection. The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals. 8.25.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.28 RTC and backup registers The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC1759/58/56/54/52/51 is designed to have extremely low power consumption, i.e. less than 1 A. The RTC will typically run from the main chip power supply, conserving battery power while the rest of the device is powered up.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC17xx usbclk (48 MHz) USB PLL MAIN OSCILLATOR USB CLOCK DIVIDER MAIN PLL pllclk system clock select (CLKSRCSEL) INTERNAL RC OSCILLATOR USB BLOCK USB clock config USB PLL enable (USBCLKCFG) cclk CPU CLOCK DIVIDER main PLL enable CPU clock config (CCLKCFG) ARM CORTEX-M3 ETHERNET BLOCK DMA GPIO NVIC WATCHDOG TIMER CCLK/8 32 kHz RTC OSCILLATOR PERIPHERAL CLOCK GENERATOR pclkWDT rtclk = 1Hz REAL-TIME CLOCK CCLK/
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.29.2 Main PLL (PLL0) The PLL0 accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU and/or the USB block. The PLL0 input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value ‘N’, which may be in the range of 1 to 256.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 8.29.5 Power control The LPC1759/58/56/54/52/51 support a variety of power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller On wake-up from Deep-sleep mode, the code execution and peripherals activities will resume after 4 cycles expire if the IRC was used before entering Deep-sleep mode. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. PLL and clock dividers need to be reconfigured accordingly. 8.29.5.
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NXP Semiconductors LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller On the LPC1759/58/56/54/52/51, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the VDD(REG)(3V3) pin powers the on-chip voltage regulator which in turn provides power to the CPU and most of the peripherals. Depending on the LPC1759/58/56/54/52/51 application, a design can use two power options to manage power consumption.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC17xx to I/O pads VDD(3V3) to core VSS REGULATOR VDD(REG)(3V3) to memories, peripherals, oscillators, PLLs MAIN POWER DOMAIN POWER SELECTOR VBAT ULTRA LOW-POWER REGULATOR BACKUP REGISTERS RTCX1 32 kHz OSCILLATOR RTCX2 REAL-TIME CLOCK RTC POWER DOMAIN DAC VDDA VREFP ADC VREFN VSSA ADC POWER DOMAIN 002aad978 Fig 5. Power distribution 8.30 System control 8.30.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.30.2 Brownout detection The LPC1759/58/56/54/52/51 include 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this voltage falls below 2.2 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.30.5 AHB multilayer matrix The LPC1759/58/56/54/52/51 use an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main (32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these memories. The peripheral DMA controllers, Ethernet (LPC1758 only) and USB, can access all SRAM blocks.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(3V3) Parameter Conditions supply voltage (3.3 V) external rail Min Max Unit [2] 0.5 +4.6 V VDD(REG)(3V3) regulator supply voltage (3.3 V) [2] 0.5 +4.6 V VDDA analog 3.3 V pad supply voltage [2] 0.5 +4.6 V Vi(VBAT) input voltage on pin VBAT [2] 0.5 +4.6 V [2] 0.5 +4.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10. Thermal characteristics 10.1 Thermal characteristics The average chip junction temperature, TJ (C), can be calculated using the following equation: T J = T amb +  P D  R th  j – a   (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11. Static characteristics Table 7. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Min Typ[1] Max Unit 2.4 3.3 3.6 V 2.4 3.3 3.6 V [3][4] 2.5 3.3 3.6 V input voltage on pin VBAT [5] 2.1 3.3 3.6 V Vi(VREFP) input voltage on pin VREFP [3] 2.5 3.3 VDDA V IDD(REG)(3V3) regulator supply current active mode; code (3.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 7. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol IDD(ADC) Parameter ADC supply current Min Typ[1] Max Unit [16][17] - 1.95 - mA [16][18] - <0.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 7. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Oscillator pins Vi(XTAL1) input voltage on pin XTAL1 0.5 1.8 1.95 V Vo(XTAL2) output voltage on pin XTAL2 0.5 1.8 1.95 V Vi(RTCX1) input voltage on pin RTCX1 0.5 - 3.6 V Vo(RTCX2) output voltage on pin RTCX2 0.5 - 3.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller [15] TCK/SWDCLK pin needs to be externally pulled LOW. [16] VDDA = 3.3 V; Tamb = 25 C. [17] The ADC is powered if the PDN bit in the AD0CR register is set to 1. See LPC17xx user manual UM10360. [18] The ADC is in Power-down mode if the PDN bit in the AD0CR register is set to 0. See LPC17xx user manual UM10360. [19] Vi(VREFP) = 3.3 V; Tamb = 25 C. [20] Including voltage on outputs in 3-state mode.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aaf569 120 IDD(Reg)(3V3) (μA) 80 3.6 V 3.3 V 2.4 V 40 0 −40 −15 10 35 60 85 temperature (°C) Conditions: VDD(Reg)(3V3) = 3.3 V; BOD disabled. Fig 7. Power-down mode: Typical regulator supply current IDD(Reg)(3V3) versus temperature 002aag119 1.8 Vi(VBAT) = 3.6 V 3.3 V 3.0 V 2.4 V IBAT) (μA) 1.4 1.0 0.6 -40 -15 10 35 60 85 temperature (°C) Conditions: VDD(REG)(3V3) floating; RTC running. Fig 8.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aag120 2.0 IDD(REG)(3V3)/IBAT (µA) IDD(REG)(3V3) 1.6 1.2 IBAT 0.8 0.4 0 -40 -15 10 35 60 85 temperature (°C) Conditions: VBAT = 3.0 V; VDD(REG)(3V3) = 3.0 V; RTC running. Fig 9.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.2 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the PCONP register. All other blocks are disabled and no code is executed. Measured on a typical sample at Tamb = 25 C. The peripheral clock PCLK = CCLK/4. Table 8.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.3 Electrical pin characteristics 002aaf112 3.6 VOH (V) T = 85 °C 25 °C −40 °C 3.2 2.8 2.4 2.0 0 8 16 24 IOH (mA) Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 10. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH 002aaf111 15 IOL (mA) T = 85 °C 25 °C −40 °C 10 5 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aaf108 10 Ipu (μA) −10 −30 T = 85 °C 25 °C −40 °C −50 −70 0 1 2 3 4 5 VI (V) Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 12. Typical pull-up current Ipu versus input voltage VI 002aaf109 90 Ipd (μA) 70 T = 85 °C 25 °C −40 °C 50 30 10 −10 0 1 2 3 4 5 VI (V) Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 13.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12. Dynamic characteristics 12.1 Flash memory Table 9. Flash characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Nendu endurance tret retention time ter erase time tprog programming time Conditions [1] Min Typ Max Unit 10000 100000 - cycles powered 10 - - years unpowered 20 - - years sector or multiple consecutive sectors 95 100 105 ms 0.95 1 1.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12.3 Internal oscillators Table 11. Dynamic characteristic: internal oscillators Tamb = 40 C to +85 C; 2.7 V  VDD(REG)(3V3)  3.6 V.[1] Symbol Parameter Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency - 3.96 4.02 4.04 MHz fi(RTC) RTC input frequency - - 32.768 - kHz [1] Parameters are valid over operating temperature range unless otherwise specified.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12.5 I2C-bus Table 13. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.[2] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz tf fall time [3][4][5][6] Fast-mode 0 400 kHz of both SDA and SCL signals - 300 ns 20 + 0.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller tf SDA tSU;DAT 70 % 30 % 70 % 30 % tHD;DAT tf 70 % 30 % SCL tVD;DAT tHIGH 70 % 30 % 70 % 30 % 70 % 30 % tLOW S 1 / fSCL 002aaf425 Fig 16. I2C-bus pins clock timing LPC1759_58_56_54_52_51 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.5 — 24 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12.6 I2S-bus interface (LPC1759/58/56 only) Table 14. Dynamic characteristics: I2S-bus interface pins Tamb = 40 C to +85 C. Symbol Parameter Conditions Min Typ Max Unit common to input and output tr rise time [1] - - 35 ns tf fall time [1] - - 35 ns tWH pulse width HIGH on pins I2STX_CLK and I2SRX_CLK [1] 0.495  Tcy(clk) - - - tWL pulse width LOW on pins I2STX_CLK and I2SRX_CLK [1] - - 0.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Tcy(clk) tf tr I2SRX_CLK tWH tWL I2SRX_SDA tsu(D) th(D) I2SRX_WS tsu(D) tsu(D) 002aae159 Fig 18. I2S-bus timing (input) LPC1759_58_56_54_52_51 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.5 — 24 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12.7 SSP interface The maximum SSP speed is 33 Mbit/s in master mode or 8 Mbit/s in slave mode. In slave mode, the maximum SSP clock rate must be 1/12 of the SSP PCLK clock rate. Table 15. Dynamic characteristics: SSP pins in SPI mode CL = 30 pF on all SSP pins; Tamb = 40 C to 85 C; VDD(3V3) = 3.3 V to 3.6 V; input slew = 1 ns; sampled at 10 % and 90 % of the signal level. Values guaranteed by design.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO th(Q) DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO DATA VALID CPHA = 1 DATA VALID th(Q) CPHA = 0 DATA VALID 002aae830 Fig 20. SSP slave timing in SPI mode LPC1759_58_56_54_52_51 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12.8 USB interface Table 16. Dynamic characteristics: USB pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD(3V3); 3.0 V  VDD(3V3)  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 % to 90 % 8.5 - 13.8 ns tf fall time 10 % to 90 % 7.7 - 13.7 ns tFRFM differential rise and fall time matching tr / tf - - 109 % VCRS output signal crossover voltage 1.3 - 2.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12.9 SPI Table 17. Dynamic characteristics of SPI pins Tamb = 40 C to +85 C. Symbol Parameter Tcy(PCLK) PCLK cycle time TSPICYC SPI cycle time tSPICLKH SPICLK HIGH time tSPICLKL SPICLK LOW time [1] Min Typ Max Unit 10 - - ns 79.6 - - ns 0.485  TSPICYC - - ns - 0.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller TSPICYC tSPICLKH tSPICLKL SCK (CPOL = 0) SCK (CPOL = 1) tSPIOH tSPIQV MOSI DATA VALID DATA VALID tSPIDSU MISO DATA VALID tSPIDH DATA VALID 002aad987 Fig 23. SPI master timing (CPHA = 0) TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH SCK (CPOL = 0) SCK (CPOL = 1) MOSI DATA VALID DATA VALID tSPIOH tSPIQV MISO DATA VALID DATA VALID 002aad988 Fig 24.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller TSPICYC tSPICLKH tSPICLKL SCK (CPOL = 0) SCK (CPOL = 1) tSPIDSU MOSI DATA VALID tSPIDH DATA VALID tSPIQV MISO tSPIOH DATA VALID DATA VALID 002aad989 Fig 25. SPI slave timing (CPHA = 0) 13. ADC electrical characteristics Table 18. ADC characteristics (full resolution) VDDA = 2.5 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 13 MHz; 12-bit resolution.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 19. ADC characteristics (lower resolution) Tamb = 40 C to +85 C unless otherwise specified; 12-bit ADC used as 10-bit resolution ADC.[1] Symbol Parameter Conditions Min Typ [2][3] Max Unit ED differential linearity error - 1 - LSB EL(adj) integral non-linearity [4] - 1.5 - LSB EO offset error [5] - 2 - LSB EG gain error [6] - 2 - LSB fclk(ADC) ADC clock frequency 3.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller offset error EO gain error EG 4095 4094 4093 4092 4091 4090 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096 VIA (LSBideal) offset error EO 1 LSB = VREFP − VREFN 4096 002aad948 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC17xx ADC COMPARATOR BLOCK C3 2.2 pF Ri2 100 Ω - 600 Ω Ri1 2 kΩ - 5.2 kΩ AD0[n] C1 750 fF C2 65 fF Cia Rvsi VSS VEXT 002aaf197 The values of resistor components Ri1 and Ri2 vary with temperature and input voltage and are process-dependent (see Table 20). Parasitic resistance and capacitance from the pad are not included in this figure. Fig 27. ADC interface to pins AD0[n] Table 20.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 15. Application information 15.1 Suggested USB interface solutions If the LPC1759/58/56/54/52/51 VDD is always greater than 0 V while VBUS = 5 V, the VBUS pin can be connected directly to the VBUS pin on the USB connector. This applies to bus powered devices where the USB cable supplies the system power.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller VDD R2 R2 LPC17xx USB_UP_LED R1 1.5 kΩ R3 USB_VBUS USB-B connector USB_D+ RS = 33 Ω USB_D- RS = 33 Ω VSS aaa-008962 Fig 29. USB interface on a bus-powered device where VBUS = 5 V, VDD not present VDD(3V3) USB_UP_LED USB_CONNECT LPC17xx SoftConnect switch R1 1.5 kΩ VBUS USB_D+ RS = 33 Ω USB-B connector USB_D− RS = 33 Ω VSS 002aad939 Fig 30.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller VDD RESET_N VBUS ADR/PSW ID RSTOUT OE_N/INT_N VDD SPEED SUSPEND LPC1759/58/ 56/54 DP 33 Ω DM 33 Ω ISP1302 VSS SCL SCL1/2 Mini-AB connector SDA SDA1/2 INT_N EINT0 USB_D+ USB_D− USB_UP_LED 002aae155 VDD Fig 31.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller VDD USB_UP_LED VDD USB_CONNECT LPC17xx VSS USB_D+ 33 Ω D+ USB_D− 33 Ω D− VBUS USB-B connector VBUS 002aad943 Fig 33. LPC1759/58/56/54/52/51 USB device port configuration 15.2 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1.8 V.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC1xxx L XTALIN XTALOUT CL = CP XTAL RS CX2 CX1 002aaf424 Fig 35. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 22.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout. 15.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 15.5 Reset pin configuration VDD VDD VDD Rpu reset ESD 20 ns RC GLITCH FILTER PIN ESD VSS 002aaf274 Fig 37. Reset pin configuration LPC1759_58_56_54_52_51 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8.5 — 24 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 15.6 ElectroMagnetic Compatibility (EMC) Radiated emission measurements according to the IEC61967-2 standard using the TEM-cell method are shown for part LPC1768. Table 24. ElectroMagnetic Compatibility (EMC) for part LPC1768 (TEM-cell method) VDD = 3.3 V; Tamb = 25 C.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 16. Package outline LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1 c y X A 60 41 40 Z E 61 e E HE A A2 (A 3) A1 w M θ bp Lp L pin 1 index 80 21 detail X 20 1 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 17. Soldering Footprint information for reflow soldering of LQFP80 package SOT315-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 15.300 15.300 12.300 12.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 12.500 12.500 15.550 15.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 18. Abbreviations Table 25.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 20. Revision history Table 26. Revision history Document ID Release date LPC1759_58_56_54_52_51 v.8.5 20140624 Modifications: - LPC1759_58_56_54_52_51 v.8.4 • • • SSP maximum bit rate in master mode corrected to 33 Mbit/s. Parameter Tj(max) added in Table 5 “Limiting values”. Description of capture channels corrected in Section 8.21.1. • • Product data sheet - LPC1759_58_56_54_52_51 v.8.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 26. Revision history …continued Document ID Modifications: LPC1759_58_56_54_52_51 v.7 Modifications: Release date Modifications: Change Supersedes notice • Remove table note “The peak current is limited to 25 times the corresponding maximum current.” from Table 4 “Limiting values”. • • • • • • • • • • • Change VDD(3V3) to VDD(REG)(3V3) in Section 11.3 “Internal oscillators”.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 21. Legal information 21.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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LPC1759/58/56/54/52/51 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10.1 11 11.1 11.2 11.3 12 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 13 14 15 15.1 15.2 15.3 15.4 15.5 15.6 16 17 18 19 20 21 21.1 21.2 21.3 21.4 22 23 Thermal characteristics. . . . . . . . . . . . . . . . . . Static characteristics. . . . . . . . . . . . . . . . . . . . Power consumption . . . . . . . . . . . . . . . . . . . . Peripheral power consumption . . . . . . . . . . . . Electrical pin characteristics . . . . . .