Datasheet

LPC1759_58_56_54_52_51 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8.5 — 24 June 2014 34 of 80
NXP Semiconductors
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
On the LPC1759/58/56/54/52/51, I/O pads are powered by the 3.3 V (V
DD(3V3)
) pins, while
the V
DD(REG)(3V3)
pin powers the on-chip voltage regulator which in turn provides power to
the CPU and most of the peripherals.
Depending on the LPC1759/58/56/54/52/51 application, a design can use two power
options to manage power consumption.
The first option assumes that power consumption is not a concern and the design ties the
V
DD(3V3)
and V
DD(REG)(3V3)
pins together. This approach requires only one 3.3 V power
supply for both pads, the CPU, and peripherals. While this solution is simple, it does not
support powering down the I/O pad ring “on the fly” while keeping the CPU and
peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (V
DD(3V3)
) and
a dedicated 3.3 V supply for the CPU (V
DD(REG)(3V3)
). Having the on-chip voltage regulator
powered independently from the I/O pad ring enables shutting down of the I/O pad power
supply “on the fly”, while the CPU and peripherals stay active.
The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of
power to operate, which can be supplied by an external battery. The device core power
(V
DD(REG)(3V3)
) is used to operate the RTC whenever V
DD(REG)(3V3)
is present. Therefore,
there is no power drain from the RTC battery when V
DD(REG)(3V3)
is available.