Datasheet

LPC1759_58_56_54_52_51 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8.5 — 24 June 2014 53 of 80
NXP Semiconductors
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
12.6 I
2
S-bus interface (LPC1759/58/56 only)
[1] CCLK = 20 MHz; peripheral clock to the I
2
S-bus interface PCLK =
CCLK
⁄
4
; T
cy(clk)
= 1600 ns, corresponds to the SCK signal in the I
2
S-bus
specification.
Table 14. Dynamic characteristics: I
2
S-bus interface pins
T
amb
=  40  C to +85  C.
Symbol Parameter Conditions Min Typ Max Unit
common to input and output
t
r
rise time
[1]
--35ns
t
f
fall time
[1]
--35ns
t
WH
pulse width HIGH on pins I2STX_CLK and
I2SRX_CLK
[1]
0.495  T
cy(clk)
-- -
t
WL
pulse width LOW on pins I2STX_CLK and
I2SRX_CLK
[1]
- - 0.505  T
cy(clk)
ns
output
t
v(Q)
data output valid time on pin I2STX_SDA;
[1]
--30ns
on pin I2STX_WS
[1]
--30ns
input
t
su(D)
data input set-up time on pin I2SRX_SDA
[1]
3.5 - - ns
t
h(D)
data input hold time on pin I2SRX_SDA
[1]
4.0 - - ns
Fig 17. I
2
S-bus timing (output)
002aad992
I2STX_CLK
I2STX_SDA
I2STX_WS
T
cy(clk)
t
f
t
r
t
WH
t
WL
t
v(Q)
t
v(Q)