Datasheet

LPC1759_58_56_54_52_51 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8.5 — 24 June 2014 56 of 80
NXP Semiconductors
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
Fig 20. SSP slave timing in SPI mode
SCK (CPOL = 0)
MOSI
MISO
T
cy(clk)
t
DS
t
DH
t
v(Q)
DATA VALID DATA VALID
t
h(Q)
SCK (CPOL = 1)
DATA VALID
DATA VALID
MOSI
MISO
t
DS
t
DH
t
v(Q)
DATA VALID DATA VALID
t
h(Q)
DATA VALID
DATA VALID
CPHA = 1
CPHA = 0
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