Datasheet

LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 82 of 122
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
[1] Parameters are shown as RD
n
or WD
n
in Figure 16 as indicated in the Conditions column.
[2] Parameters specified for 40 % of V
DD(3V3)
for rising edges and 60 % of V
DD(3V3)
for falling edges.
[3] T
cy(clk)
= 1/EMC_CLK (see LPC178x/7x User manual UM10470).
[4] Latest of address valid, EMC_CSx
LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1).
[5] After End Of Read (EOR): Earliest of EMC_CSx
HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid.
[6] End Of Write (EOW): Earliest of address invalid, EMC_CSx
HIGH, EMC_BLSx HIGH (PB = 1).
t
deact
deactivation time WR
8
; PB = 0;
PB = 1
[3]
2.7 3.4 4.7 ns
t
CSLBLSL
CS LOW to BLS LOW WR
9
; PB = 0
[3]
2.8 + T
cy(clk)

(1 + WAITWEN)
3.7 + T
cy(clk)

(1 + WAITWEN)
5.1 + T
cy(clk)

(1 + WAITWEN)
ns
t
BLSLBLSH
BLS LOW to BLS HIGH
time
WR
10
; PB = 0
[3]
(WAITWR 
WAITWEN + 3) 
T
cy(clk)
 2.6
(WAITWR 
WAITWEN + 3) 
T
cy(clk)
 3.4
(WAITWR 
WAITWEN + 3) 
T
cy(clk)
 4.9
ns
t
BLSHEOW
BLS HIGH to end of
write time
WR
11
; PB = 0
[3][6]
2.6 + T
cy(clk)
3.3 + T
cy(clk)
4.4 + T
cy(clk)
ns
t
BLSHDNV
BLS HIGH to data
invalid time
WR12;
PB = 0
[3]
2.7 + T
cy(clk)
3.6 + T
cy(clk)
4.8 + T
cy(clk)
ns
Table 17. Dynamic characteristics: Static external memory interface
…continued
C
L
=30pF, T
amb
=  40  C to 85  C, V
DD(3V3)
= 3.0 V to 3.6 V. Values guaranteed by design.
Symbol Parameter
[1]
Conditions
[1]
Min Typ Max Unit
Fig 16. External static memory read/write access (PB = 0)
RD
1
RD
5
RD
2
WR
2
WR
9
WR
12
WR
10
WR
11
RD
5
RD
5
RD
6
WR
8
WR
1
EOR
EOW
RD
7
RD
4
EMC_Ax
EMC_CSx
EMC_OE
EMC_BLSx
EMC_WE
EMC_Dx
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