Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LBGA 256 (17x17) 32-Bit 180 MHz I/O number 164

1. General description

The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embedded

applications. The ARM Cortex-M3 is a next generation core that offers system

enhancements such as low power consumption, enhanced debug features, and a high

level of support block integration.

The LPC1850/30/20/10 operate at CPU frequencies of up to 180 MHz. The ARM

Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with

separate local instruction and data buses as well as a third bus for peripherals. The ARM

Cortex-M3 CPU also includes an internal prefetch unit that supports speculative

branching.

The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM, a quad SPI Flash

Interface (SPIFI), a State Configurable Timer/PWM (SCTimer/PWM) subsystem, two

High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple

digital and analog peripherals.

See Section 17 “

References” for additional documentation.

2. Features and benefits

 Processor core

 ARM Cortex-M3 processor (version r2p1), running at frequencies of up to

180 MHz.

 ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.

 ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

 Non-maskable Interrupt (NMI) input.

 JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.

 Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.

 System tick timer.

 On-chip memory

 200 kB SRAM for code and data use.

 Multiple SRAM blocks with separate bus access.

 64 kB ROM containing boot code and on-chip software drivers.

 64 bit + 256 bit One-Time Programmable (OTP) memory for general-purpose use.

 Clock generation unit

 Crystal oscillator with an operating range of 1 MHz to 25 MHz.

 12 MHz internal RC oscillator trimmed to 1.5 % accuracy over temperature and

voltage.

LPC1850/30/20/10

32-bit ARM Cortex-M3 flashless MCU; up to 200 kB SRAM;

Ethernet, two HS USB, LCD, and external memory controller

Rev. 6.4 — 18 August 2014 Product data sheet

Summary of content (150 pages)

PAGE 1
LPC1850/30/20/10 32-bit ARM Cortex-M3 flashless MCU; up to 200 kB SRAM; Ethernet, two HS USB, LCD, and external memory controller Rev. 6.4 — 18 August 2014 Product data sheet 1. General description The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embedded applications. The ARM Cortex-M3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller  Ultra-low power RTC crystal oscillator.  Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the third PLL can be used as audio PLL.  Clock output.  Configurable digital peripherals:  State Configurable Timer (SCTimer/PWM) subsystem on AHB.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller      Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources.  Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.  Four general-purpose timer/counters with capture and match capabilities.  One motor control PWM for three-phase motor control.  One Quadrature Encoder Interface (QEI).
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 4. Ordering information Table 1.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 5.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 6. Pinning information 6.1 Pinning LPC1850/30FET256 ball A1 index area 2 1 4 3 6 5 8 7 10 9 12 11 14 13 LPC1850/30FET180 ball A1 index area 16 2 1 15 A 4 3 6 5 8 7 10 9 12 11 A B B C C D D E E F G F J H L K G H K J M L N M P N R P T 002aag365 002aaf230 Transparent top view Transparent top view Fig 2. 14 13 Pin configuration LBGA256 package Fig 3.
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LPC1850/30/20/10 NXP Semiconductors 73 108 32-bit ARM Cortex-M3 microcontroller 109 72 LPC1830/20/10FBD144 Fig 5. 36 37 1 144 002aag368 Pin configuration LQFP144 package 6.2 Pin description On the LPC1850/30/20/10, digital pins are grouped into 16 ports, named P0 to P9 and PA to PF, with up to 20 pins used per port. Each digital pin can support up to eight different digital functions, including General-Purpose I/O (GPIO), selectable through the System Configuration Unit (SCU) registers.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Type 32 Description [1] LQFP144 G2 Reset state TFBGA100 LBGA256 Symbol TFBGA180 Table 3. Pin description LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. Multiplexed digital pins P0_0 P0_1 L3 M2 K3 K2 G1 34 [2] [2] N; PU I/O GPIO0[0] — General purpose digital input/output pin. I/O SSP1_MISO — Master In Slave Out for SSP1.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LQFP144 N1 K2 42 [2] Type TFBGA100 R2 Description [1] TFBGA180 P1_1 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O O CTOUT_7 — SCTimer/PWM output 7. Match output 3 of timer 1. I/O EMC_A6 — External memory address line 6. - R — Function reserved. - R — Function reserved.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P1_6 P1_7 LQFP144 N3 J4 48 T4 T5 P3 N4 K4 G4 49 50 [2] [2] [2] Type TFBGA100 R5 Description [1] TFBGA180 P1_5 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O GPIO1[8] — General purpose digital input/output pin. O CTOUT_10 — SCTimer/PWM output 10. Match output 3 of timer 3.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P1_9 LQFP144 M5 H5 51 T7 N5 J5 52 [2] [2] Type TFBGA100 R7 Description [1] TFBGA180 P1_8 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O O U1_DTR — Data Terminal Ready output for UART1. O CTOUT_12 — SCTimer/PWM output 12. Match output 3 of timer 3. I/O EMC_D1 — External memory data line 1.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P1_13 P1_14 P1_15 LQFP144 P7 K7 56 R10 R11 T12 LPC1850_30_20_10 Product data sheet L8 K7 P11 H8 J8 K8 60 61 62 [2] [2] [2] [2] Type TFBGA100 R9 Description [1] TFBGA180 P1_12 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O GPIO1[5] — General purpose digital input/output pin.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P1_17 LQFP144 L5 H9 64 M8 L6 H10 66 [2] [3] Type TFBGA100 M7 Description [1] TFBGA180 P1_16 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O I U2_RXD — Receiver input for USART2. - R — Function reserved. I ENET_CRS — Ethernet Carrier Sense (MII interface). O T0_MAT0 — Match output 0 of timer 0.
PAGE 14
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P2_0 K10 70 T16 N14 G10 75 [2] [2] Type J10 Description [1] TFBGA100 M10 LQFP144 TFBGA180 P1_20 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O GPIO0[15] — General purpose digital input/output pin. I/O SSP1_SSEL — Slave Select for SSP1. - R — Function reserved.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P2_3 LQFP144 L13 F5 84 J12 G11 D8 87 [2] [3] Type TFBGA100 M15 Description [1] TFBGA180 P2_2 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU - R — Function reserved. I/O U0_UCLK — Serial clock input/output for USART0 in synchronous mode. I/O EMC_A11 — External memory address line 11.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller D10 91 [3] Type J12 Description [1] TFBGA100 K14 LQFP144 TFBGA180 P2_5 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU - R — Function reserved. I CTIN_2 — SCTimer/PWM input 2. Capture input 2 of timer 0. I USB1_VBUS — Monitors the presence of USB1 bus power.
PAGE 17
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LQFP144 H14 C6 98 [2] Type TFBGA100 J16 Description [1] TFBGA180 P2_8 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU O CTOUT_0 — SCTimer/PWM output 0. Match output 0 of timer 0. I/O U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. I/O EMC_A8 — External memory address line 8.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P2_13 P3_0 LQFP144 D13 B9 106 C16 F13 LPC1850_30_20_10 Product data sheet E14 D12 A10 108 A8 112 [2] [2] [2] Type TFBGA100 E15 Description [1] TFBGA180 P2_12 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O GPIO1[12] — General purpose digital input/output pin. O CTOUT_4 — SCTimer/PWM output 4.
PAGE 19
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P3_2 P3_3 LQFP144 D10 F7 114 F11 B14 LPC1850_30_20_10 Product data sheet D9 B13 G6 A7 116 118 [2] [2] [4] Type TFBGA100 G11 Description [1] TFBGA180 P3_1 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave.
PAGE 20
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P3_5 P3_6 P3_7 LQFP144 C14 B8 119 C12 B13 C11 LPC1850_30_20_10 Product data sheet C11 B12 C10 B7 C7 D7 121 122 123 [2] [2] [2] [2] Type TFBGA100 A15 Description [1] TFBGA180 P3_4 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O GPIO1[14] — General purpose digital input/output pin.
PAGE 21
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P4_0 P4_1 P4_2 LQFP144 C9 E7 124 D5 A1 D3 LPC1850_30_20_10 Product data sheet D4 D3 A2 - - - 1 3 8 [2] [2] [5] [2] Type TFBGA100 C10 Description [1] TFBGA180 P3_8 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU - R — Function reserved. - R — Function reserved.
PAGE 22
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P4_4 LQFP144 B2 - 7 B1 A1 - 9 [5] [5] Type TFBGA100 C2 Description [1] TFBGA180 P4_3 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O GPIO2[3] — General purpose digital input/output pin. O CTOUT_3 — SCTimer/PWM output 3. Match output 3 of timer 0. O LCD_VD2 — LCD data. - R — Function reserved.
PAGE 23
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LQFP144 B1 - 11 [2] Type TFBGA100 C1 Description [1] TFBGA180 P4_6 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O O CTOUT_4 — SCTimer/PWM output 4. Match output 3 of timer 3. O LCD_ENAB/LCDM — STN AC bias drive or TFT data enable input. - R — Function reserved. - R — Function reserved.
PAGE 24
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P5_0 P5_1 P5_2 LQFP144 L3 - 35 N3 P3 R4 LPC1850_30_20_10 Product data sheet L2 M1 M3 - - - 37 39 46 [2] [2] [2] [2] Type TFBGA100 M3 Description [1] TFBGA180 P4_10 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU - R — Function reserved. I CTIN_2 — SCTimer/PWM input 2.
PAGE 25
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P5_4 P5_5 P5_6 LQFP144 P6 - 54 P9 P10 T13 LPC1850_30_20_10 Product data sheet N7 N8 M11 - - - 57 58 63 [2] [2] [2] [2] Type TFBGA100 T8 Description [1] TFBGA180 P5_3 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O GPIO2[12] — General purpose digital input/output pin.
PAGE 26
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P6_0 P6_1 P6_2 LQFP144 N11 - 65 M12 R15 L13 LPC1850_30_20_10 Product data sheet M10 H7 P14 K11 G5 J9 73 74 78 [2] [2] [2] [2] Type TFBGA100 R12 Description [1] TFBGA180 P5_7 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O GPIO2[7] — General purpose digital input/output pin.
PAGE 27
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LQFP144 N13 - 79 [2] Type TFBGA100 P15 Description [1] TFBGA180 P6_3 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O O GPIO3[2] — General purpose digital input/output pin.
PAGE 28
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P6_7 P6_8 P6_9 LQFP144 K12 - 83 J13 H13 J15 LPC1850_30_20_10 Product data sheet H11 F12 H13 - - F8 85 86 97 [2] [2] [2] [2] Type TFBGA100 L14 Description [1] TFBGA180 P6_6 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O GPIO0[5] — General purpose digital input/output pin.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P6_11 P6_12 P7_0 LQFP144 G13 - 100 H12 G15 B16 LPC1850_30_20_10 Product data sheet F11 F13 B14 C9 - - 101 103 110 [2] [2] [2] [2] Type TFBGA100 H15 Description [1] TFBGA180 P6_10 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O GPIO3[6] — General purpose digital input/output pin.
PAGE 30
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P7_2 P7_3 LQFP144 C13 - 113 A16 C13 LPC1850_30_20_10 Product data sheet A14 C12 - - 115 117 [2] [2] [2] Type TFBGA100 C14 Description [1] TFBGA180 P7_1 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O GPIO3[9] — General purpose digital input/output pin. O CTOUT_15 — SCTimer/PWM output 15.
PAGE 31
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P7_5 P7_6 LQFP144 C6 - 132 A7 C7 LPC1850_30_20_10 Product data sheet A7 F5 - - 133 134 [5] [5] [2] Type TFBGA100 C8 Description [1] TFBGA180 P7_4 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O GPIO3[12] — General purpose digital input/output pin. O CTOUT_13 — SCTimer/PWM output 13.
PAGE 32
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P8_0 P8_1 P8_2 LQFP144 D5 - 140 E5 H5 K4 LPC1850_30_20_10 Product data sheet E4 G4 J4 - - - - - - [5] [3] [3] [3] Type TFBGA100 B6 Description [1] TFBGA180 P7_7 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O GPIO3[15] — General purpose digital input/output pin.
PAGE 33
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P8_4 P8_5 P8_6 LQFP144 H3 - - J2 J1 K3 LPC1850_30_20_10 Product data sheet H2 H1 J3 - - - - - - [2] [2] [2] [2] Type TFBGA100 J3 Description [1] TFBGA180 P8_3 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O GPIO4[3] — General purpose digital input/output pin.
PAGE 34
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P8_8 P9_0 P9_1 LQFP144 J1 - - L1 T1 N6 LPC1850_30_20_10 Product data sheet K1 P1 P4 - - - - - - [2] [2] [2] [2] Type TFBGA100 K1 Description [1] TFBGA180 P8_7 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O GPIO4[7] — General purpose digital input/output pin.
PAGE 35
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P9_3 LQFP144 M6 - - M6 P5 - - [2] [2] Type TFBGA100 N8 Description [1] TFBGA180 P9_2 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O O MCOB2 — Motor control PWM channel 2, output B. - R — Function reserved. - R — Function reserved. I/O I2S0_TX_SDA — I2S transmit data.
PAGE 36
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PA_0 PA_1 PA_2 LQFP144 M9 - 72 L12 J14 K15 LPC1850_30_20_10 Product data sheet L10 H12 J13 - - - - - - [2] [2] [3] [3] Type TFBGA100 L11 Description [1] TFBGA180 P9_6 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O GPIO4[11] — General purpose digital input/output pin.
PAGE 37
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PA_4 PB_0 PB_1 LQFP144 E10 - - G13 B15 A14 E12 D14 A13 - - - - - - [3] [2] [2] [2] Type TFBGA100 H11 Description [1] TFBGA180 PA_3 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O I QEI_PHA — Quadrature Encoder Interface PHA input. - R — Function reserved. - R — Function reserved.
PAGE 38
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PB_3 PB_4 PB_5 LQFP144 B11 - - A13 B11 A12 LPC1850_30_20_10 Product data sheet A12 B10 A11 - - - - - - [2] [2] [2] [2] Type TFBGA100 B12 Description [1] TFBGA180 PB_2 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU - R — Function reserved.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PC_0 PC_1 PC_2 LQFP144 C5 - - D4 E4 F6 LPC1850_30_20_10 Product data sheet - - - - - - - - - [5] [5] [2] [2] Type TFBGA100 A6 Description [1] TFBGA180 PB_6 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU - R — Function reserved. I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3.
PAGE 40
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PC_4 LQFP144 - - - F4 - - - [5] [2] Type TFBGA100 F5 Description [1] TFBGA180 PC_3 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5. - R — Function reserved. O U1_RTS — Request to Send output for UART1.
PAGE 41
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PC_8 PC_9 LQFP144 - - - N4 K2 - - - - - - [2] [2] [2] Type TFBGA100 G5 Description [1] TFBGA180 PC_7 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1. - R — Function reserved. I ENET_RXD3 — Ethernet receive data 3 (MII interface).
PAGE 42
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PC_12 PC_13 PC_14 LQFP144 - - - L6 M1 N1 LPC1850_30_20_10 Product data sheet - - - - - - - - - [2] [2] [2] [2] Type TFBGA100 L5 Description [1] TFBGA180 PC_11 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU - R — Function reserved. I USB1_ULPI_DIR — ULPI link DIR signal.
PAGE 43
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PD_1 PD_2 PD_3 LQFP144 - - - P1 R1 P4 LPC1850_30_20_10 Product data sheet - - - - - - - - - [2] [2] [2] [2] Type TFBGA100 N2 Description [1] TFBGA180 PD_0 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU - R — Function reserved. O CTOUT_15 — SCTimer/PWM output 15. Match output 3 of timer 3.
PAGE 44
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PD_5 PD_6 PD_7 LQFP144 - - - P6 R6 T6 - - - - - - - - - [2] [2] [2] [2] Type TFBGA100 T2 Description [1] TFBGA180 PD_4 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU O CTOUT_8 — SCTimer/PWM output 8. Match output 0 of timer 2. I/O EMC_D18 — External memory data line 18.
PAGE 45
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PD_9 PD_10 LQFP144 - - - T11 P11 - - - - - - [2] [2] [2] Type TFBGA100 P8 Description [1] TFBGA180 PD_8 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU I CTIN_6 — SCTimer/PWM input 6. Capture input 1 of timer 3. I/O EMC_D22 — External memory data line 22. - R — Function reserved.
PAGE 46
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PD_13 PD_14 PD_15 LQFP144 P9 - - T14 R13 T15 LPC1850_30_20_10 Product data sheet - L11 P13 - - - - - - [2] [2] [2] [2] Type TFBGA100 N11 Description [1] TFBGA180 PD_12 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU - R — Function reserved. - R — Function reserved.
PAGE 47
LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PE_0 PE_1 PE_2 LQFP144 P12 - - P14 N14 M14 LPC1850_30_20_10 Product data sheet N12 - M12 - L12 - - - - [2] [2] [2] [2] Type TFBGA100 R14 Description [1] TFBGA180 PD_16 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU - R — Function reserved. - R — Function reserved.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PE_4 PE_5 PE_6 LQFP144 K10 - - K13 N16 M16 LPC1850_30_20_10 Product data sheet J11 - - - - - - - - [2] [2] [2] [2] Type TFBGA100 K12 Description [1] TFBGA180 PE_3 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU - R — Function reserved. O CAN0_TD — CAN transmitter output.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PE_8 PE_9 PE_10 LQFP144 - - - F14 E16 E14 LPC1850_30_20_10 Product data sheet - - - - - - - - - [2] [2] [2] [2] Type TFBGA100 F15 Description [1] TFBGA180 PE_7 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU - R — Function reserved. O CTOUT_5 — SCTimer/PWM output 5.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PE_12 PE_13 PE_14 LQFP144 - - - D15 G14 C15 LPC1850_30_20_10 Product data sheet - - - - - - - - - [2] [2] [2] [2] Type TFBGA100 D16 Description [1] TFBGA180 PE_11 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU - R — Function reserved. O CTOUT_12 — SCTimer/PWM output 12.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PF_0 PF_1 PF_2 LQFP144 - - - D12 E11 D11 LPC1850_30_20_10 Product data sheet - - - - - - - - - [2] [2] [2] [2] Type TFBGA100 E13 Description [1] TFBGA180 PE_15 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU - OL; PU R — Function reserved. O CTOUT_0 — SCTimer/PWM output 0.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PF_4 PF_5 LQFP144 - - - D10 E9 LPC1850_30_20_10 Product data sheet D6 - H4 - 120 - [2] [2] [5] Type TFBGA100 E10 Description [1] TFBGA180 PF_3 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU - OL; PU R — Function reserved. I U3_RXD — Receiver input for USART3.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PF_7 PF_8 LQFP144 - - - B7 E6 LPC1850_30_20_10 Product data sheet - - - - - - [5] [5] [5] Type TFBGA100 E7 Description [1] TFBGA180 PF_6 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU - R — Function reserved. I/O U3_DIR — RS-485/EIA-485 output enable/direction control for USART3.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PF_10 PF_11 LQFP144 - - - A3 A2 LPC1850_30_20_10 Product data sheet - - - - - - [5] [5] [5] Type TFBGA100 D6 Description [1] TFBGA180 PF_9 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. N; PU - R — Function reserved. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller TFBGA100 LQFP144 M4 K3 45 Type TFBGA180 N5 Description [1] LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. Clock pins CLK0 CLK1 CLK2 CLK3 T10 D14 P12 LPC1850_30_20_10 Product data sheet - P10 - - K6 - - 99 - [4] [4] [4] [4] O; PU O EMC_CLK0 — SDRAM clock 0. O CLKOUT — Clock output pin.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller TFBGA100 LQFP144 K4 A6 28 Type TFBGA180 L4 Description [1] LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. Debug pins DBGEN [2] I; PU I JTAG interface control signal. Also used for boundary scan. To use the part in functional mode, connect this pin in one of the following ways: • Leave DBGEN open.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LQFP144 A9 A9 A4 130 [11] I; IA I External wake-up input; can raise an interrupt and can cause wake-up from any of the low-power modes. A pulse with a duration of at least 45 ns wakes up the part. This pin does not have an external pull-up. WAKEUP1 A10 C8 - - [11] I; IA I External wake-up input; can raise an interrupt and can cause wake-up from any of the low-power modes.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. D1 16 - - Separate analog 3.3 V power supply for driver. USB0 _VDDA3V3 G3 F3 D2 17 - - USB 3.3 V separate power supply voltage. USB0_VSSA _TERM H3 G3 D3 19 - - Dedicated analog ground for clean reference for termination resistors.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller VSSIO C4, D13, G6, G7, G8, H8, H9, J8, J9, K9, K10, M13, P7, P13 - 4, 40, 76, 109 VSSA B2 A3 C2 B9 B8 - [13] Type Description [1] Reset state LQFP144 TFBGA100 LBGA256 Symbol TFBGA180 Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. - - Ground. 135 - - Analog ground. - - - n.c.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7. Functional description 7.1 Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus. The I-code and D-code core buses allow for concurrent code and data accesses from different slave ports. The LPC1850/30/20/10 use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and other bus masters to peripherals.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but can have several interrupt flags. Individual interrupt flags can also represent more than one interrupt source. 7.6 Event router The event router combines various internal signals, interrupts, and the external interrupt pins (WAKEUP[3:0]) to create an interrupt in the NVIC, if enabled.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.8.1 ISP (In-System Programming) mode In-System Programming (ISP) means programming or reprogramming the on-chip SRAM memory, using the boot loader software and the USART0 serial port. ISP can be performed when the part resides in the end-user board. ISP loads data into on-chip SRAM and execute code from on-chip SRAM. 7.9 Boot ROM The internal ROM memory is used to store the boot code of the LPC1850/30/20/10.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 5. Boot mode when OPT BOOT_SRC bits are zero Boot mode Pins Description P2_9 P2_8 P1_2 P1_1 USART0 LOW LOW LOW LOW Boot from device connected to USART0 using pins P2_0 and P2_1. SPIFI LOW LOW LOW HIGH Boot from Quad SPI flash connected to the SPIFI interface on P3_3 to P3_8[1]. EMC 8-bit LOW LOW HIGH LOW Boot from external static memory (such as NOR flash) using CS0 and an 8-bit data bus.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.11 One-Time Programmable (OTP) memory The OTP provides 64 bit + 256 bit of memory for general-purpose use. 7.12 General-Purpose I/O (GPIO) The LPC1850/30/20/10 provides eight GPIO ports with up to 31 GPIO pins each. Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • • • • • 7.13.1.1 Clock selection Inputs Events Outputs Interrupts Features • • • • • • • • Two 16-bit counters or one 32-bit counter. Counters clocked by bus clock or selected input. Counters can be configured as up counters or up-down counters. State variable allows sequencing across multiple counter cycles. Event combines input or output condition and/or counter match in a specified state.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Two AHB bus masters for transferring data. These interfaces transfer data when a DMA request goes active. Master 1 can access memories and peripherals, master 0 can access memories only. • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • MultiMedia Cards (MMC version 4.4) 7.13.5 External Memory Controller (EMC) The LPC1850/30/20/10 EMC is a Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and NOR flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. 7.13.5.1 Features • Dynamic memory interface support including single data rate SDRAM.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • • • • • • Complies with USB On-The-Go supplement. Complies with Enhanced Host Controller Interface Specification. Supports auto USB 2.0 mode discovery. Supports all high-speed USB-compliant peripherals. Supports all full-speed USB-compliant peripherals. Supports software Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for OTG peripherals. • Supports interrupts. • This module has its own, integrated DMA engine.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Setup and control via a separate AHB slave interface. • Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data. • Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays with 4-bit or 8-bit interfaces. • Supports single and dual-panel color STN displays. • Supports Thin Film Transistor (TFT) color displays.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.14 Digital serial peripherals 7.14.1 UART The LPC1850/30/20/10 contain one UART with standard transmit and receive data lines. UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. UART1 includes a fractional baud rate generator.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Smart card mode conforming to ISO7816 specification 7.14.3 SSP serial I/O controller Remark: The LPC1850/30/20/10 contain two SSP controllers. The SSP controller can operate on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. • All I2C-bus controllers support multiple address recognition and a bus monitor mode. 7.14.5 I2S interface Remark: The LPC1850/30/20/10 contain two I2S interfaces. The I2S-bus provides a standard communication interface for digital audio applications.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Provides programmable FIFO mode (concatenation of Message Objects). • Provides maskable interrupts. • Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN applications. • Provides programmable loop-back mode for self-test operation. 7.15 Counter/timers and motor control 7.15.1 General purpose 32-bit timers/external event counter Remark: The LPC1850/30/20/10 include four 32-bit timer/counters.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, the QEI can capture the velocity of the encoder wheel. 7.15.3.1 Features • • • • • • • • • • Tracks encoder position.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • • • • Incorrect feed sequence causes reset or interrupt if enabled. Flag to indicate watchdog reset. Programmable 24-bit timer with internal prescaler.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.17.1.1 Features • Measures the passage of time to maintain a calendar and clock. Provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. • Ultra-low power design to support battery powered systems. Uses power from the CPU power supply when it is present. • • • • • Dedicated battery power supply pin. RTC power supply is isolated from the rest of the chip.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.18.3 Clock Generation Unit (CGU) The Clock Generator Unit (CGU) generates several base clocks. The base clocks can be unrelated in frequency and phase and can have different clock sources within the CGU. One CGU base clock is routed to the CLKOUT pins. The base clock that generates the CPU clock is referred to as CCLK. Multiple branch clocks are derived from each base clock.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.18.8 Reset Generation Unit (RGU) The RGU allows generation of independent reset signals for individual blocks and peripherals. 7.18.9 Power control The LPC1850/30/20/10 feature several independent power domains to control power to the core and the peripherals (see Figure 9).
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller The LPC1850/30/20/10 can wake up from Deep-sleep, Power-down, and Deep power-down modes via the WAKEUP[3:0] pins and interrupts generated by battery powered blocks in the RTC power domain. 7.19 Emulation and debugging Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(REG)(3V3) regulator supply voltage (3.3 V) on pin VDDREG 0.5 3.6 V VDD(IO) input/output supply voltage on pin VDDIO 0.5 3.6 V VDDA(3V3) analog supply voltage (3.3 V) on pin VDDA 0.5 3.6 V VBAT battery supply voltage on pin VBAT 0.5 3.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 9. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb +  P D  R th  j – a   (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD(REG)(3V3) and VDD(REG)(3V3).
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10. Static characteristics Table 10. Static characteristics Tamb = 40 C to +85 C unless otherwise specified. Symbol Parameter Min Typ[1] Max Unit 2.2 - 3.6 V 2.2 - 3.6 V on pin VDDA 2.2 - 3.6 V on pins USB0_VDDA3V3_ DRIVER and USB0_VDDA3V3 3.0 3.3 3.6 V Conditions Supply pins VDD(IO) input/output supply voltage VDD(REG)(3V3) regulator supply voltage (3.3 V) VDDA(3V3) analog supply voltage (3.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 10. Static characteristics …continued Tamb = 40 C to +85 C unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IDD(IO) I/O supply current deep sleep mode - 1 - A - 1 - A [8] - 0.05 - A [11] - 0.4 - power-down mode deep power-down mode IDDA Analog supply current on pin VDDA; A deep sleep mode power-down mode [11] - 0.4 - deep power-down mode [11] - 0.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 10. Static characteristics …continued Tamb = 40 C to +85 C unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IOL LOW-level output current VOL = 0.4 V 6 - - mA IOHS HIGH-level short-circuit drive HIGH; connected to output current ground [12] - - 86.5 mA IOLS LOW-level short-circuit output current drive LOW; connected to VDD(IO) [12] - - 76.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 10. Static characteristics …continued Tamb = 40 C to +85 C unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit I/O pins - high drive strength: standard drive mode IOH HIGH-level output current VOH = VDD(IO)  0.4 V 4 - - mA IOL LOW-level output current VOL = 0.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 10. Static characteristics …continued Tamb = 40 C to +85 C unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IOZ OFF-state output current VO = 0 V to VDD(IO); on-chip pull-up/down resistors disabled; absolute value - 3 - nA VI input voltage pin configured to provide a digital function; VDD(IO)  2.2 V 0 - 5.5 V VDD(IO) = 0 V 0 - 3.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 10. Static characteristics …continued Tamb = 40 C to +85 C unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Oscillator pins Vi(XTAL1) input voltage on pin XTAL1 0.5 - 1.2 V Vo(XTAL2) output voltage on pin XTAL2 0.5 - 1.2 V Cio input/output capacitance - - 0.8 pF VDD(IO)  2.2 V 0 - 5.25 V VDD(IO) = 0 V 0 - 3.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller [5] PLL1 disabled; IRC running; CCLK = 12 MHz. [6] VBAT = 3.6 V. [7] VDD(IO) = VDDA = 3.6 V; over entire frequency range CCLK = 12 MHz to 180 MHz. [8] VDD(REG)(3V3) = 3.3 V; VDD(IO) = 3.3 V. Input leakage increases when VDD(IO) is floating or grounded. It is recommended to keep VDD(REG)(3V3) and VDD(IO) powered in deep power-down mode. [9] On pin VBAT; Tamb = 25 C.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10.1 Power consumption 002aah592 80 IDD(REG)(3V3) (mA) (mA) 180 MHz 60 120 MHz 40 60 MHz 20 12 MHz 0 2.2 2.4 2.6 2.8 3 3.2 3.4 VDD(REG)(3V3) (V) 3.6 Conditions: Tamb = 25 C; active mode entered executing code while(1){} from SRAM; internal pull-up resistors disabled; PLL1 enabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled. Fig 10.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aah594 100 IDD(REG)(3V3) IDD(REG)(3V3) (mA) (mA) 85 °C C 25 °C C -40 °C C 80 60 40 20 0 12 36 60 84 108 132 156 CCLK frequency (MHz) 180 Conditions: VDD(REG)(3V3) = 3.3 V; Active mode entered executing code while(1){} from SRAM; internal pull-up resistors disabled; PLL1 enabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled. Fig 12.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aah154 300 IDD(REG)(3V3) )( (μA) 240 180 120 60 0 -40 -15 10 35 60 temperature (°C) 85 Conditions: VDD(REG)(3V3) = 3.3 V; VBAT floating; VDD(IO) = 3.3 V. Fig 14. Typical supply current versus temperature in Deep-sleep mode 002aah155 50 IDD(REG)(3V3) )( (μA) 40 30 20 10 0 -40 -15 10 35 60 temperature (°C) 85 Conditions: VDD(REG)(3V3) = 3.3 V; VBAT floating; VDD(IO) = 3.3 V. Fig 15.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aah156 10 IDD(REG)(3V3) DD(REG (μA) 8 6 4 2 0 -40 -15 10 35 60 temperature (°C) 85 Conditions: VDD(REG)(3V3) = 3.3 V; VBAT floating; VDD(IO) = 3.3 V. Fig 16. Typical supply current versus temperature in Deep power-down mode 002aah150 80 IBAT (μA) 60 40 20 0 -0.4 -0.2 0 0.2 0.4 VBAT - VDD(REG)(3V3) (V) 0.6 Conditions: VDD(REG)(3V3) = 3.0 V; CCLK = 12 MHz. Fig 17.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aah157 10 IBAT (μA) 8 6 VBAT = 3.6 V 3.0 V 2.2 V 4 2 0 -40 -15 10 35 60 temperature (°C) 85 Conditions: VDD(REG)(3V3), VDD(IO) floating. Fig 18. Typical battery supply versus temperature in Deep power-down mode 10.2 Peripheral power consumption The typical power consumption at T = 25 C for each individual peripheral is measured as follows: 1. Enable all branch clocks and measure the current IDD(REG)(3V3). 2.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 11. Peripheral power consumption Peripheral LPC1850_30_20_10 Product data sheet Branch clock IDD(REG)(3V3) in mA Branch clock frequency = 48 MHz Branch clock frequency = 96 MHz ETHERNET CLK_M3_ETHERNET 1.05 2.09 UART0 CLK_M3_UART0, CLK_APB0_UART0 0.3 0.38 UART1 CLK_M3_UART1, CLK_APB0_UART1 0.27 0.48 UART2 CLK_M3_UART2, CLK_APB2_UART2 0.27 0.47 UART3 CLK_M3_USART3, CLK_APB2_UART3 0.29 0.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10.3 BOD characteristics Table 12. BOD static characteristics[1] Tamb = 25 C; typical data. Symbol Parameter Conditions Vth threshold voltage interrupt level 0 Min Typ Max Unit assertion - 2.75 - V de-assertion - 2.92 - V assertion - 2.85 - V de-assertion - 3.00 - V assertion - 2.95 - V de-assertion - 3.12 - V assertion - 3.05 - V de-assertion - 3.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10.4 Electrical pin characteristics 002aah030 15 -40 °C 25 °C 85 °C IOL (mA) 12 9 6 3 0 0 0.1 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V. Fig 19. Normal-drive pins and high-speed pins; typical LOW level output current IOL versus LOW level output voltage VOL 002aah039 3.6 VOH (V) 3.2 2.8 T = 85 °C 25 °C -40 °C 2.4 2.0 0 12 24 36 IOH (mA) Conditions: VDD(REG)(3V3) = VDD(IO) = 3.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aah040 15 -40 °C 25 °C 85 °C IOL (mA) 12 002aah041 25 IOL (mA) 20 9 15 6 10 3 5 0 -40 °C 25 °C 85 °C 0 0 0.1 0.2 0.3 0.4 0.5 VOL (V) 0.6 0 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; normal-drive; EHD = 0x0. 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; medium-drive; EHD = 0x1. 002aah043 40 IOL (mA) 0.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aah047 3.6 VOH (V) 002aah048 3.6 VOH (V) 3.2 3.2 -40 °C 25 °C 85 °C 2.8 -40 °C 25 °C 85 °C 2.8 2.4 2.4 2.0 2.0 0 8 16 24 0 16 32 IOH (mA) Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; normal-drive; EHD = 0x0. 002aah049 3.6 48 IOH (mA) VOH (V) Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; medium-drive; EHD = 0x1. 002aah050 3.6 VOH (V) 3.2 3.2 -40 °C 25 °C 85 °C 2.8 -40 °C 25 °C 85 °C 2.8 2.4 2.4 2.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aah450 20 Ipu Ipu (μA) 0 +85 °C +25 °C -40 °C -20 -40 -60 -80 0 1 2 3 4 VI (V) 5 Conditions: VDD(IO) = 3.3 V. Simulated values. Fig 23. Typical pull-up current Ipu versus input voltage VI 002aah449 120 IIpd pd (μA) -40 °C +25 °C +85 °C 90 60 30 0 0 1 2 3 4 VI (V) 5 Conditions: VDD(IO) = 3.3 V. Simulated values. Fig 24.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11. Dynamic characteristics 11.1 Wake-up times Table 13.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.3 Crystal oscillator Table 15. Dynamic characteristic: oscillator Tamb = 40 C to +85 C; VDD(IO) over specified ranges; 2.2 V  VDD(REG)(3V3)  3.6 V.[1] Symbol Parameter Conditions Low-frequency mode (1 MHz to 20 tjit(per) period jitter time period jitter time Typ[2] Max Unit MHz)[5] 5 MHz crystal [3][4] - 13.2 - ps 10 MHz crystal - 6.6 - ps 15 MHz crystal - 4.8 - ps - 4.3 - ps - 3.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.6 I/O pins Table 18. Dynamic characteristic: I/O pins[1] Tamb = 40 C to +85 C; 2.7 V  VDD(IO)  3.6 V. Symbol Parameter Conditions Min Typ Max Unit Standard I/O pins - normal drive strength tr rise time pin configured as output; EHS = 1 [2][3] 1.0 - 2.5 ns tf fall time pin configured as output; EHS = 1 [2][3] 0.9 - 2.5 ns pin configured as output; EHS = 0 [2][3] 1.9 - 4.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.7 I2C-bus Table 19. Dynamic characteristic: I2C-bus pins Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V.[1] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz [3][4][5][6] fall time tf Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz of both SDA and SCL signals - 300 ns Fast-mode 20 + 0.1  Cb 300 ns Fast-mode Plus - 120 ns Standard-mode 4.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller tf SDA tSU;DAT 70 % 30 % 70 % 30 % tHD;DAT tf 70 % 30 % SCL tVD;DAT tHIGH 70 % 30 % 70 % 30 % 70 % 30 % tLOW 1 / fSCL S 002aaf425 Fig 26. I2C-bus pins clock timing 11.8 I2S-bus interface Table 20. Dynamic characteristics: I2S-bus interface pins Tamb = 25 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Conditions and data refer to I2S0 and I2S1 pins. Simulated values.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Tcy(clk) tf tr I2Sx_TX_SCK tWH tWL I2Sx_TX_SDA tv(Q) I2Sx_TX_WS 002aag497 tv(Q) Fig 27. I2S-bus timing (transmit) Tcy(clk) tf tr I2Sx_RX_SCK tWH tWL I2Sx_RX_SDA tsu(D) th(D) I2Sx_RX_WS tsu(D) 002aag498 tsu(D) Fig 28. I2S-bus timing (receive) 11.9 USART interface Table 21. Dynamic characteristics: USART interface Tamb = 25 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Simulated values.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.10 SSP interface Table 22. Dynamic characteristics: SSP pins in SPI mode Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Simulated values. Symbol Tcy(clk) Parameter clock cycle time Conditions Min Typ Max Unit - 40 - ns when only transmitting - 20 - ns [1] full-duplex mode SSP master tDS data set-up time in SPI mode 13.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 22. Dynamic characteristics: SSP pins in SPI mode Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Simulated values. Symbol Parameter Conditions Min Typ Max Unit td delay time continuous transfer mode - 0.5 Tcy(clk) - - SPI mode; CPOL = 0; CPHA = 1 - n/a - - SPI mode; CPOL = 1; CPHA = 0 - 0.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) SSEL MOSI (CPHA = 0) tv(Q) th(Q) DATA VALID (MSB) DATA VALID DATA VALID (MSB) DATA VALID (LSB) DATA VALID (MSB) IDLE tDH tDS MISO (CPHA = 0) MOSI (CPHA = 1) td tlag tlead DATA VALID DATA VALID (MSB) DATA VALID (LSB) tv(Q) th(Q) DATA VALID (LSB) DATA VALID tDS MISO (CPHA = 1) DATA VALID (LSB) DATA VALID (MSB) IDLE DATA VALID (MSB) tDH DATA VALID DATA VALID (MSB) DA
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO th(Q) DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO DATA VALID CPHA = 1 DATA VALID th(Q) CPHA = 0 DATA VALID 002aae830 Fig 30. SSP slave timing in SPI mode LPC1850_30_20_10 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.11 External memory interface Table 23. Dynamic characteristics: Static asynchronous external memory interface CL = 22 pF for EMC_Dn CL = 20 pF for all others; Tamb = 40 C to 85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; values guaranteed by design. Timing parameters are given for single memory access cycles.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 23. Dynamic characteristics: Static asynchronous external memory interface …continued CL = 22 pF for EMC_Dn CL = 20 pF for all others; Tamb = 40 C to 85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; values guaranteed by design. Timing parameters are given for single memory access cycles. In a normal read operation, the EMC changes the address while CS is asserted resulting in multiple memory accesses.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller EMC_An tCSLAV tCSLAV tOEHANV tCSHEOW EMC_CSn tCSLOEL tOELOEH EMC_OE tCSLBLSL tCSHOEH tCSLBLSL EMC_BLSn tCSHBLSH tCSLWEL tWELWEH tWEHEOW EMC_WE tBLSHDNV tam tCSHEOR th(D) tCSLSOR tCSLDV tWEHDNV EMC_Dn SOR EOR EOW 002aag700 Fig 32. External static memory read/write access (PB = 1) LPC1850_30_20_10 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 24. Dynamic characteristics: Dynamic external memory interface Simulated data over temperature and process range; CL = 10 pF for EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE, EMC_An; CL = 9 pF for EMC_Dn; CL = 5 pF for EMC_DQMOUTn, EMC_CLKn, EMC_CKEOUTn; Tamb = 40 C to 85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; VDD(IO) =3.3 V  10 %; RD = 1 (see LPC18xx User manual); EMC_CLKn delays CLK0_DELAY = CLK1_DELAY = CLK2_DELAY = CLK3_DELAY = 0.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller EMC_CLKn delay > 0 EMC_CLKn delay td; programmable CLKn_DELAY Tcy(clk) EMC_CLKn delay = 0 td(xV) - td EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE, EMC_CKEOUTn, EMC_A[22:0], EMC_DQMOUTn td(xV) th(x) - td th(x) td(QV) - td td(QV) th(Q) - td th(Q) EMC_D[31:0] write tsu(D) th(D) EMC_D[31:0] read; delay > 0 tsu(D) th(D) EMC_D[31:0] read; delay = 0 002aag703 For the programmable EMC_CLK[3:0] clock delays CLKn_DELAY, see Table 25.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.12 USB interface Table 26. Dynamic characteristics: USB0 and USB1 pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD(IO); 3.0 V  VDD(IO)  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 % to 90 % 8.5 - 13.8 ns tf fall time 10 % to 90 % 7.7 - 13.7 ns tFRFM differential rise and fall time matching tr / tf - - 109 % VCRS output signal crossover voltage 1.3 - 2.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Static characteristics: USB0 PHY pins[1] Table 27. Symbol Parameter Conditions Min Typ Max Unit - 68 - mW total supply current - 18 - mA during transmit - 31 - mA during receive - 14 - mA with driver tri-stated - 14 - mA - 7 - mA - 15 - mW High-speed mode Pcons IDDA(3V3) analog supply current (3.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 28. Dynamic characteristics: Ethernet Tamb = 40 C to 85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. Values guaranteed by design.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.14 SD/MMC Table 29. Dynamic characteristics: SD/MMC Tamb = 40 C to 85 C, 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V, CL = 20 pF. Simulated values. SAMPLE_DELAY = 0x8, DRV_DELAY = 0xF in the SDDELAY register (see the LPC18xx user manual UM10430). Symbol Parameter Conditions Max Unit 52 MHz 0.5 2 ns 0.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.16 SPIFI Table 31. Dynamic characteristics: SPIFI Tamb = 40 C to 85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. CL = 10 pF. Simulated values. Symbol Parameter Min Max Unit Tcy(clk) clock cycle time 9.6 - ns tDS data set-up time 3.4 - ns tDH data hold time 0 - ns tv(Q) data output valid time - 3.2 ns th(Q) data output hold time 0.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12. ADC/DAC electrical characteristics Table 32. ADC characteristics VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VIA analog input voltage 0 - VDDA(3V3) V Cia analog input capacitance - - 2 pF ED differential linearity error - 0.8 - LSB - 1.0 - LSB 2.7 V  VDDA(3V3)  3.6 V [1][2] 2.2 V  VDDA(3V3) < 2.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = VDDA(3V3) − VSSA 1024 002aaf959 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Rvsi LPC18xx 2 kΩ (analog pin) 2.2 kΩ (multiplexed pin) ADC0_n/ADC1_n Rs ADC COMPARATOR Cia = 2 pF VEXT VSS 002aag697 Rs < 1/((7  fclk(ADC)  Cia)  2 k Fig 39. ADC interface to pins Table 33. DAC characteristics VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; unless otherwise specified Symbol Parameter Conditions ED differential linearity error 2.7 V  VDDA(3V3)  3.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 13. Application information 13.1 LCD panel signal usage Table 34.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 35.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 36.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 37. Recommended values for CX1/X2 in oscillation mode (crystal and external components parameters) low frequency mode Fundamental oscillation frequency Maximum crystal series resistance RS External load capacitors CX1, CX2 12 MHz < 160  18 pF, 18 pF < 160  39 pF, 39 pF 16 MHz < 120  18 pF, 18 pF < 80  33 pF, 33 pF < 100  18 pF, 18 pF < 80  33 pF, 33 pF 20 MHz Table 38.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 13.3 RTC oscillator In the RTC oscillator circuit, only the crystal (XTAL) and the capacitances CRTCX1 and CRTCX2 need to be connected externally. Typical capacitance values for CRTCX1 and CRTCX2 are CRTCX1/2 = 20 (typical)  4 pF. An external clock can be connected to RTCX1 if RTCX2 is left open. The recommended amplitude of the clock signal is Vi(RMS) = 100 mV to 200 mV with a coupling capacitance of 5 pF to 10 pF.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller VDDIO ESD enable output driver data output from core PIN slew rate bit EHS input buffer enable bit EZI data input to core glitch filter filter select bit ZIF pull-up enable bit EPUN ESD pull-down enable bit EPD analog I/O VSSIO 002aah028 The glitch filter rejects pulses of typical 12 ns width. Fig 43. Standard I/O pin configuration with analog input 13.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller On the LPC1850/30/20/10, USBn_VBUS pins are 5 V tolerant only when VDDIO is applied and at operating voltage level. Therefore, if the USBn_VBUS function is connected to the USB connector and the device is self-powered, the USBn_VBUS pins must be protected for situations when VDDIO = 0 V. If VDDIO is always at operating level while VBUS = 5 V, the USBn_VBUS pin can be connected directly to the VBUS pin on the USB connector.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC18xx VDDREG REGULATOR USBn_VBUS VBUS USB-B connector USB aaa-013016 Fig 46. USB interface on a bus-powered device Remark: If the VBUS function of the USB1 interface is not connected, configure the pin function for GPIO using the function control bits in the SYSCON block. VDDIO R1 LPC18xx T2 R2 T1 R3 USBn_VBUS VBUS USB-B connector USB aaa-013017 Fig 47.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 14.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller TFBGA180: thin fine-pitch ball grid array package; 180 balls SOT570-3 A B D ball A1 index area E A2 A A1 detail X e1 e 1/2 e ∅v ∅w b M M C C A B C y y1 C P N M L K J H G F E D C B A ball A1 index area e e2 1/2 e 1 2 3 4 5 6 7 8 9 10 11 12 13 X 14 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A A1 A2 b D E e e1 e2 v w y y1 1.20 1.06 0.95 0.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm B D SOT926-1 A ball A1 index area A2 E A A1 detail X e1 e ∅v ∅w b 1/2 e C M M C A B C y y1 C K J e H G F e2 E D 1/2 e C B A ball A1 index area 1 2 3 4 5 6 7 8 9 10 X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 b D E e e1 e2 v w y y1 mm 1.2 0.4 0.3 0.8 0.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1 c y X A 73 72 108 109 ZE e E HE A A2 (A 3) A1 θ wM Lp bp L pin 1 index detail X 37 144 1 36 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 20.1 19.9 0.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 15. Soldering Footprint information for reflow soldering of LBGA256 package SOT740-2 Hx P P Hy see detail X Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste SL SP occupied area SR solder resist detail X DIMENSIONS in mm P SL SP SR 1.00 0.450 0.450 0.600 Hx Hy 17.500 17.500 sot740-2_fr Fig 52.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of TFBGA180 package SOT570-3 Hx P P Hy see detail X Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste SL SP occupied area SR solder resist detail X DIMENSIONS in mm P SL SP SR 0.80 0.400 0.400 0.550 Hx Hy 12.575 12.575 sot570-3_fr Fig 53.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of LQFP144 package SOT486-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 23.300 23.300 20.300 20.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 20.500 20.500 23.550 23.550 sot486-1_fr Fig 54.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of TFBGA100 package SOT926-1 Hx P P Hy see detail X Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste SL SP occupied area SR solder resist detail X DIMENSIONS in mm P SL SP SR Hx Hy 0.80 0.330 0.400 0.480 9.400 9.400 sot926-1_fr Fig 55.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 16. Abbreviations Table 39.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 39. Abbreviations …continued Acronym Description USART Universal Synchronous Asynchronous Receiver/Transmitter USB Universal Serial Bus UTMI USB 2.0 Transceiver Macrocell Interface 17. References LPC1850_30_20_10 Product data sheet [1] LPC18xx User manual UM10430: http://www.nxp.com/documents/user_manual/UM10430.pdf [2] LPC18X0 Errata sheet: http://www.nxp.com/documents/errata_sheet/ES_LPC18X0.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 18. Revision history Table 40. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC1850_30_20_10 v.6.4 20140818 - Modifications: Product data sheet LPC1850_30_20_10 v.6.3 • IEEE standard 802.3 compliance added to Section 11.13. Covers Ethernet dynamic characteristics of ENET_MDIO and ENET_MDC signals. • Parameter CI corrected for high-drive pins (changed from 2 pF to 5.2 pF).
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 40. Revision history …continued Document ID Release date Data sheet status Change notice Supersedes LPC1850_30_20_10 v.6.2 20131014 - Modifications: LPC1850_30_20_10 v.6.1 Modifications: LPC1850_30_20_10 Product data sheet Product data sheet LPC1850_30_20_10 v.6.1 • Parameter ILH (High-level leakage current) for condition VI = 5 V changed to 20 nA (max). See Table 10.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 40. Revision history …continued Document ID Release date Data sheet status Change notice Supersedes LPC1850_30_20_10 v.6 20121011 - Modifications: Product data sheet LPC1850_30_20_10 v.5.2 • Temperature range for simulated timing characteristics corrected to Tamb = 40 C to +85 C in Section 11 “Dynamic characteristics”. • • • • • SPIFI timing added. See Section 11.15.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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LPC1850/30/20/10 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 21. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.5.1 7.5.2 7.6 7.7 7.7.1 7.8 7.8.1 7.9 7.10 7.11 7.12 7.12.1 7.13 7.13.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Ordering options . . . . . . . . . .
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NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 10 10.1 10.2 10.3 10.4 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 11.14 11.15 11.16 12 13 13.1 13.2 13.3 13.4 13.5 13.6 13.7 14 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 Static characteristics. . . . . . . . . . . . . . . . . . . . 85 Power consumption . . . . . . . . . . . . . . . . . . . . 92 Peripheral power consumption . . . . . . . . . . . . 96 BOD characteristics . . . . . . . . . . . . . . . . . .