Datasheet

LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6.4 — 18 August 2014 26 of 150
NXP Semiconductors
LPC1850/30/20/10
32-bit ARM Cortex-M3 microcontroller
P5_7 R12 N11 - 65
[2]
N; PU I/O GPIO2[7] — General purpose digital input/output pin.
O MCOA2 — Motor control PWM channel 2, output A.
I/O EMC_D11 — External memory data line 11.
- R — Function reserved.
I U1_RXD — Receiver input for UART1.
O T1_MAT3 — Match output 3 of timer 1.
- R — Function reserved.
- R — Function reserved.
P6_0 M12 M10 H7 73
[2]
N; PU - R — Function reserved.
O I2S0_RX_MCLK — I
2
S receive master clock.
- R — Function reserved.
- R — Function reserved.
I/O I2S0_RX_SCK — Receive Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I
2
S-bus specification.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
P6_1 R15 P14 G5 74
[2]
N; PU I/O GPIO3[0] — General purpose digital input/output pin.
O EMC_DYCS1
— SDRAM chip select 1.
I/O U0_UCLK — Serial clock input/output for USART0 in
synchronous mode.
I/O I2S0_RX_WS — Receive Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I
2
S-bus specification.
- R — Function reserved.
I T2_CAP0 — Capture input 2 of timer 2.
- R — Function reserved.
- R — Function reserved.
P6_2 L13 K11 J9 78
[2]
N; PU I/O GPIO3[1] — General purpose digital input/output pin.
O EMC_CKEOUT1 — SDRAM clock enable 1.
I/O U0_DIR — RS-485/EIA-485 output enable/direction control for
USART0.
I/O I2S0_RX_SDA — I
2
S Receive data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I
2
S-bus specification.
- R — Function reserved.
I T2_CAP1 — Capture input 1 of timer 2.
- R — Function reserved.
- R — Function reserved.
Table 3. Pin description
…continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256 TFBGA180 TFBGA100 LQFP144 Reset state [1] Type
Description