Datasheet

LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6.4 — 18 August 2014 61 of 150
NXP Semiconductors
LPC1850/30/20/10
32-bit ARM Cortex-M3 microcontroller
7.4 AHB multilayer matrix
7.5 Nested Vectored Interrupt Controller (NVIC)
The NVIC is part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt
latency and efficient processing of late arriving interrupts.
7.5.1 Features
• Controls system exceptions and peripheral interrupts.
• On the LPC1850/30/20/10, the NVIC supports 53 vectored interrupts.
• Eight programmable interrupt priority levels, with hardware priority level masking.
• Relocatable vector table.
• Non-Maskable Interrupt (NMI).
• Software interrupt generation.
(1) Not available on all parts (see Tab le 2).
Fig 6. AHB multilayer matrix master and slave connections
ARM
CORTEX-M3
TEST/DEBUG
INTERFACE
DMA ETHERNET
(1)
USB1
(1)
USB0
(1)
LCD
(1)
SD/
MMC
EXTERNAL
MEMORY
CONTROLLER
AHB REGISTER
INTERFACES,
APB, RTC DOMAIN
PERIPHERALS
32 kB AHB SRAM
16 kB AHB SRAM
(1)
16 kB AHB SRAM
slaves
64 kB ROM
64/96 kB LOCAL SRAM
40 kB LOCAL SRAM
System
bus
I-code
bus
D-code
bus
masters
01
SPIFI
AHB MULTILAYER MATRIX
= master-slave connection
002aag550