Datasheet

LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6.4 — 18 August 2014 64 of 150
NXP Semiconductors
LPC1850/30/20/10
32-bit ARM Cortex-M3 microcontroller
[1] The boot loader programs the appropriate pin function at reset to boot using the SSP0 or SPIFI.
Remark: Pin functions for SPIFI and SSP0 boot are different.
Table 5. Boot mode when OPT BOOT_SRC bits are zero
Boot mode Pins Description
P2_9 P2_8 P1_2 P1_1
USART0 LOW LOW LOW LOW Boot from device connected to USART0
using pins P2_0 and P2_1.
SPIFI LOW LOW LOW HIGH Boot from Quad SPI flash connected to
the SPIFI interface on P3_3 to P3_8
[1]
.
EMC 8-bit LOW LOW HIGH LOW Boot from external static memory (such
as NOR flash) using CS0 and an 8-bit
data bus.
EMC 16-bit LOW LOW HIGH HIGH Boot from external static memory (such
as NOR flash) using CS0 and a 16-bit
data bus.
EMC 32-bit LOW HIGH LOW LOW Boot from external static memory (such
as NOR flash) using CS0 and a 32-bit
data bus.
USB0 LOW HIGH LOW HIGH Boot from USB0
USB1 LOW HIGH HIGH LOW Boot from USB1.
SPI (SSP0) LOW HIGH HIGH HIGH Boot from SPI flash connected to the
SSP0 interface on P3_3 (function
SSP0_SCK), P3_6 (function
SSP0_SSEL), P3_7 (function
SSP0_MISO), and P3_8 (function
SSP0_MOSI)
[1]
.
USART3 HIGH LOW LOW LOW Boot from device connected to USART3
using pins P2_3 and P2_4.