Datasheet

LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6.4 — 18 August 2014 81 of 150
NXP Semiconductors
LPC1850/30/20/10
32-bit ARM Cortex-M3 microcontroller
7.18.8 Reset Generation Unit (RGU)
The RGU allows generation of independent reset signals for individual blocks and
peripherals.
7.18.9 Power control
The LPC1850/30/20/10 feature several independent power domains to control power to
the core and the peripherals (see Figure 9
). The RTC and its associated peripherals (the
alarm timer, the CREG block, the OTP controller, the back-up registers, and the event
router) are located in the RTC power-domain. The main regulator or a battery supply can
power the RTC. A power selector switch ensures that the RTC block is always powered
on.
The LPC1850/30/20/10 support four reduced power modes: Sleep, Deep-sleep,
Power-down, and Deep power-down.
Fig 9. LPC1850/30/20/10 power domains
REAL-TIME CLOCK
BACKUP REGISTERS
RESET/WAKE-UP
CONTROL
REGULATOR
32 kHz
OSCILLATOR
ALWAYS-ON/RTC POWER DOMAIN
MAIN POWER DOMAIN
RTCX1
VBAT
VDDREG
RTCX2
VDDIO
VSS
to memories,
peripherals,
oscillators,
PLLs
to core
to I/O pads
ADC
DAC
OTP
ADC POWER DOMAIN
OTP POWER DOMAIN
USB0 POWER DOMAIN
VDDA
VSSA
VPP
USB0
USB0_VDDA3V3_DRIVER
USB0_VDDA3V3
LPC18xx
ULTRA LOW-POWER
REGULATOR
ALARM
RESET
WAKEUP0/1/2/3
to RTC
domain
peripherals
002aag305
to RTC I/O
pads (V
ps
)