Datasheet

LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6.4 — 18 August 2014 93 of 150
NXP Semiconductors
LPC1850/30/20/10
32-bit ARM Cortex-M3 microcontroller
Conditions: V
DD(REG)(3V3)
= 3.3 V; Active mode entered executing code while(1){} from SRAM;
internal pull-up resistors disabled; PLL1 enabled; IRC enabled; all peripherals disabled; all
peripheral clocks disabled.
Fig 12. Typical supply current versus frequency in Active mode
Conditions: V
DD(REG)(3V3)
= 3.3 V; internal pull-up resistors disabled; PLL1 enabled; IRC enabled;
all peripherals disabled; all peripheral clocks disabled; core clock CCLK = 12 MHz.
Fig 13. Typical supply current versus temperature in Sleep mode
002aah594
12 36 60 84 108 132 156 180
0
20
40
60
80
100
CCLK frequency (MHz)
IDD(REG)(3V3)
IDD(REG)(3V3)
I
DD(REG)(3V3)
(mA)
(mA)
(mA)
85 C
85 C
85 °C
25 C
25 C
25 °C
-40 C
-40 C
-40 °C
002aah153
-40 -15 10 35 60 85
0
2
4
6
8
10
temperature (°C)
I
DD(REG)(3V3)
(
(
(mA)