Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LBGA 256 (17x17) 32-Bit 180 MHz I/O number 164

1. General description

The LPC185x/3x/2x/1x are ARM Cortex-M3 based microcontrollers for embedded

applications. The ARM Cortex-M3 is a next generation core that offers system

enhancements such as low power consumption, enhanced debug features, and a high

level of support block integration.

The LPC185x/3x/2x/1x operate at CPU frequencies of up to 180 MHz. The ARM

Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with

separate local instruction and data buses as well as a third bus for peripherals. The ARM

Cortex-M3 CPU also includes an internal prefetch unit that supports speculative

branching.

The LPC185x/3x/2x/1x include up to 1 MB of flash and 136 kB of on-chip SRAM, 16 kB of

EEPROM memory, a quad SPI Flash Interface (SPIFI), a State-configurable Timer/PWM

(SCTimer/PWM) subsystem, two High-speed USB controllers, Ethernet, LCD, an external

memory controller, and multiple digital and analog peripherals.

For additional documentation related to the LPC18xx parts, see Section 17 “

References”.

2. Features and benefits

 Processor core

 ARM Cortex-M3 processor, running at CPU frequencies of up to 180 MHz.

 ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.

 ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

 Non-maskable Interrupt (NMI) input.

 JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.

 Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.

 System tick timer.

 On-chip memory

 Up to 1 MB on-chip dual bank flash memory with flash accelerator.

 16 kB on-chip EEPROM data memory.

 136 kB SRAM for code and data use.

 Multiple SRAM blocks with separate bus access.

 64 kB ROM containing boot code and on-chip software drivers.

 64 bit+ 256 bit of One-Time Programmable (OTP) memory for general-purpose

use.

 Clock generation unit

 Crystal oscillator with an operating range of 1 MHz to 25 MHz.

LPC185x/3x/2x/1x

32-bit ARM Cortex-M3 MCU; up to 1 MB flash and 136 kB

SRAM; Ethernet, two High-speed USB, LCD, EMC

Rev. 4.1 — 6 May 2014 Product data sheet

Summary of content (148 pages)

PAGE 1
LPC185x/3x/2x/1x 32-bit ARM Cortex-M3 MCU; up to 1 MB flash and 136 kB SRAM; Ethernet, two High-speed USB, LCD, EMC Rev. 4.1 — 6 May 2014 Product data sheet 1. General description The LPC185x/3x/2x/1x are ARM Cortex-M3 based microcontrollers for embedded applications. The ARM Cortex-M3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration.
PAGE 2
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller  12 MHz internal RC oscillator trimmed to 3 % accuracy over temperature and voltage (1.5 % accuracy for Tamb = 0 °C to 85 °C).  Ultra-low power RTC crystal oscillator.  Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL can be used with the High-speed USB, the third PLL can be used as audio PLL.  Clock output.
PAGE 3
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller      GPIO registers are located on the AHB for fast access. GPIO ports have DMA support.  Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources.  Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.  Four general-purpose timer/counters with capture and match capabilities.
PAGE 4
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2 LPC1857JET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2 LPC1857JBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28  28  1.
PAGE 5
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 4.1 Ordering options GPIO Temperature range[1] ADC channels QEI PWM USB1 (Host, Device)/ ULPI interface USB0 (Host, Device, OTG) Ethernet LCD Total SRAM Flash bank B Flash total Flash bank A Ordering options Type number Table 2.
PAGE 6
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 5.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 6. Pinning information 6.1 Pinning LPC185x/3xFET256 ball A1 index area 2 1 4 3 6 5 8 7 10 9 12 11 14 13 ball A1 index area 16 LPC183x/2x/1xFET100 1 15 A 2 3 4 5 6 7 8 A B C B E C D F D G E H J F L G K M H N J P R K T 002aah356 002aag541 Transparent top view Transparent top view 104 109 LPC1857/53FBD208 Fig 4.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 0 on ADC0 and channel 0 on ADC1, channel 1 inputs (named ADC0_1 and ADC1_1) are tied together and connected to channel 1 on ADC0 and ADC1, and so forth. There are eight ADC channels total for the two ADCs. Type 47 Description [1] 32 Reset state LQFP208 LBGA256 Pin name LQFP144 Pin description TFBGA100 Table 3.
PAGE 9
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P1_2 P1_3 P1_4 LQFP208 K2 42 58 R3 P5 T3 LPC185X_3X_2X_1X Product data sheet K1 J1 J2 43 44 47 60 61 64 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 R2 Description [1] TFBGA100 P1_1 LBGA256 Pin name Reset state Table 3. I/O GPIO0[8] — General purpose digital input/output pin. External boot pin (see Table 5). O CTOUT_7 — SCTimer/PWM output 7.
PAGE 10
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P1_6 P1_7 LQFP208 J4 48 65 T4 T5 LPC185X_3X_2X_1X Product data sheet K4 G4 49 50 67 69 [2] [2] [2] N; PU N; PU N; PU Type LQFP144 R5 Description [1] TFBGA100 P1_5 LBGA256 Pin name Reset state Table 3. I/O GPIO1[8] — General purpose digital input/output pin. O CTOUT_10 — SCTimer/PWM output 10. Match output 3 of timer 3. - R — Function reserved.
PAGE 11
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P1_9 P1_10 P1_11 LQFP208 H5 51 71 T7 R8 T9 LPC185X_3X_2X_1X Product data sheet J5 H6 J7 52 53 55 73 75 77 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 R7 Description [1] TFBGA100 P1_8 LBGA256 Pin name Reset state Table 3. I/O GPIO1[1] — General purpose digital input/output pin. O U1_DTR — Data Terminal Ready output for UART1.
PAGE 12
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P1_13 P1_14 P1_15 LQFP208 K7 56 78 R10 R11 T12 LPC185X_3X_2X_1X Product data sheet H8 J8 K8 60 61 62 83 85 87 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 R9 Description [1] TFBGA100 P1_12 LBGA256 Pin name Reset state Table 3. I/O GPIO1[5] — General purpose digital input/output pin. I U1_DCD — Data Carrier Detect input for UART1.
PAGE 13
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P1_17 P1_18 P1_19 LQFP208 H9 64 90 M8 N12 M11 LPC185X_3X_2X_1X Product data sheet H10 J10 K9 66 67 68 93 95 96 [2] [3] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 M7 Description [1] TFBGA100 P1_16 LBGA256 Pin name Reset state Table 3. I/O GPIO0[3] — General purpose digital input/output pin. I U2_RXD — Receiver input for USART2. - R — Function reserved.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P2_0 P2_1 LQFP208 K10 70 100 T16 N15 LPC185X_3X_2X_1X Product data sheet G10 G7 75 81 108 116 [2] [2] [2] N; PU N; PU N; PU Type LQFP144 M10 Description [1] TFBGA100 P1_20 LBGA256 Pin name Reset state Table 3. I/O GPIO0[15] — General purpose digital input/output pin. I/O SSP1_SSEL — Slave Select for SSP1. - R — Function reserved.
PAGE 15
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P2_3 P2_4 LQFP208 F5 84 121 J12 K11 LPC185X_3X_2X_1X Product data sheet D8 D9 87 88 127 128 [2] [3] [3] N; PU N; PU N; PU Type LQFP144 M15 Description [1] TFBGA100 P2_2 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I/O U0_UCLK — Serial clock input/output for USART0 in synchronous mode. I/O EMC_A11 — External memory address line 11.
PAGE 16
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued LQFP208 D10 91 131 [3] N; PU Type LQFP144 K14 Description [1] TFBGA100 P2_5 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I CTIN_2 — SCTimer/PWM input 2. Capture input 2 of timer 0. I USB1_VBUS — Monitors the presence of USB1 bus power. Note: This signal must be HIGH for USB reset to occur.
PAGE 17
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P2_9 P2_10 P2_11 LQFP208 C6 98 140 H16 G16 F16 LPC185X_3X_2X_1X Product data sheet B10 E8 A9 102 104 105 144 146 148 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 J16 Description [1] TFBGA100 P2_8 LBGA256 Pin name Reset state Table 3. - R — Function reserved. External boot pin (see Table 5) O CTOUT_0 — SCTimer/PWM output 0. Match output 0 of timer 0.
PAGE 18
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P2_13 P3_0 LQFP208 B9 106 153 C16 F13 LPC185X_3X_2X_1X Product data sheet A10 A8 108 112 156 161 [2] [2] [2] N; PU N; PU N; PU Type LQFP144 E15 Description [1] TFBGA100 P2_12 LBGA256 Pin name Reset state Table 3. I/O GPIO1[12] — General purpose digital input/output pin. O CTOUT_4 — SCTimer/PWM output 4. Match output 3 of timer 3. - R — Function reserved.
PAGE 19
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P3_2 P3_3 LQFP208 F7 114 163 F11 B14 LPC185X_3X_2X_1X Product data sheet G6 A7 116 118 166 169 [2] [2] [4] N; PU OL; PU N; PU Type LQFP144 G11 Description [1] TFBGA100 P3_1 LBGA256 Pin name Reset state Table 3. I/O I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification.
PAGE 20
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P3_5 P3_6 P3_7 LQFP208 B8 119 171 C12 B13 C11 LPC185X_3X_2X_1X Product data sheet B7 C7 D7 121 122 123 173 174 176 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 A15 Description [1] TFBGA100 P3_4 LBGA256 Pin name Reset state Table 3. I/O GPIO1[14] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved.
PAGE 21
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P4_0 P4_1 P4_2 LQFP208 E7 124 179 D5 A1 D3 LPC185X_3X_2X_1X Product data sheet - - - 1 3 8 1 3 12 [2] [2] [5] [2] N; PU N; PU N; PU N; PU Type LQFP144 C10 Description [1] TFBGA100 P3_8 LBGA256 Pin name Reset state Table 3. - R — Function reserved. - R — Function reserved. I/O SSP0_MOSI — Master Out Slave in for SSP0.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P4_4 LQFP208 - 7 10 B1 - 9 14 [5] [5] N; PU N; PU Type LQFP144 C2 Description [1] TFBGA100 P4_3 LBGA256 Pin name Reset state Table 3. I/O GPIO2[3] — General purpose digital input/output pin. O CTOUT_3 — SCTimer/PWM output 3. Match output 3 of timer 0. O LCD_VD2 — LCD data. - R — Function reserved. - R — Function reserved. O LCD_VD21 — LCD data.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P4_7 P4_8 P4_9 LQFP208 - 11 17 H4 E2 L2 LPC185X_3X_2X_1X Product data sheet - - - 14 15 33 21 23 48 [2] [2] [2] [2] N; PU O; PU N; PU N; PU Type LQFP144 C1 Description [1] TFBGA100 P4_6 LBGA256 Pin name Reset state Table 3. I/O GPIO2[6] — General purpose digital input/output pin. O CTOUT_4 — SCTimer/PWM output 4. Match output 3 of timer 3.
PAGE 24
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P5_0 P5_1 P5_2 LQFP208 - 35 51 N3 P3 R4 LPC185X_3X_2X_1X Product data sheet - - - 37 39 46 53 55 63 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 M3 Description [1] TFBGA100 P4_10 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I CTIN_2 — SCTimer/PWM input 2. Capture input 2 of timer 0. O LCD_VD10 — LCD data. - R — Function reserved.
PAGE 25
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P5_4 P5_5 P5_6 LQFP208 - 54 76 P9 P10 T13 LPC185X_3X_2X_1X Product data sheet - - - 57 58 63 80 81 89 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 T8 Description [1] TFBGA100 P5_3 LBGA256 Pin name Reset state Table 3. I/O GPIO2[12] — General purpose digital input/output pin. I MCI0 — Motor control PWM channel 0, input.
PAGE 26
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P6_0 P6_1 P6_2 LQFP208 - 65 91 M12 R15 L13 LPC185X_3X_2X_1X Product data sheet H7 G5 J9 73 74 78 105 107 111 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 R12 Description [1] TFBGA100 P5_7 LBGA256 Pin name Reset state Table 3. I/O GPIO2[7] — General purpose digital input/output pin. O MCOA2 — Motor control PWM channel 2, output A.
PAGE 27
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P6_4 P6_5 P6_6 LQFP208 - 79 113 R16 P16 L14 LPC185X_3X_2X_1X Product data sheet F6 F9 - 80 82 83 114 117 119 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 P15 Description [1] TFBGA100 P6_3 LBGA256 Pin name Reset state Table 3. I/O GPIO3[2] — General purpose digital input/output pin.
PAGE 28
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P6_8 P6_9 P6_10 LQFP208 - 85 123 H13 J15 H15 LPC185X_3X_2X_1X Product data sheet - F8 - 86 97 100 125 139 142 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 J13 Description [1] TFBGA100 P6_7 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I/O EMC_A15 — External memory address line 15. - R — Function reserved.
PAGE 29
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P6_12 P7_0 P7_1 LQFP208 C9 101 143 G15 B16 C14 LPC185X_3X_2X_1X Product data sheet - - - 103 110 113 145 158 162 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 H12 Description [1] TFBGA100 P6_11 LBGA256 Pin name Reset state Table 3. I/O GPIO3[7] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved.
PAGE 30
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P7_3 P7_4 LQFP208 - 115 165 C13 C8 LPC185X_3X_2X_1X Product data sheet - - 117 132 167 189 [2] [2] [5] N; PU N; PU N; PU Type LQFP144 A16 Description [1] TFBGA100 P7_2 LBGA256 Pin name Reset state Table 3. I/O GPIO3[10] — General purpose digital input/output pin. I CTIN_4 — SCTimer/PWM input 4. Capture input 2 of timer 1. I/O I2S0_TX_SDA — I2S transmit data.
PAGE 31
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P7_6 P7_7 LQFP208 - 133 191 C7 B6 LPC185X_3X_2X_1X Product data sheet - - 134 140 194 201 [5] [2] [5] N; PU N; PU N; PU Type LQFP144 A7 Description [1] TFBGA100 P7_5 LBGA256 Pin name Reset state Table 3. I/O GPIO3[13] — General purpose digital input/output pin. O CTOUT_12 — SCTimer/PWM output 12. Match output 3 of timer 3. - R — Function reserved.
PAGE 32
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P8_1 P8_2 P8_3 LQFP208 - - 2 H5 K4 J3 LPC185X_3X_2X_1X Product data sheet - - - - - - 34 36 37 [3] [3] [3] [2] N; PU N; PU N; PU N; PU Type LQFP144 E5 Description [1] TFBGA100 P8_0 LBGA256 Pin name Reset state Table 3. I/O GPIO4[0] — General purpose digital input/output pin.
PAGE 33
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P8_5 P8_6 P8_7 LQFP208 - - 39 J1 K3 K1 LPC185X_3X_2X_1X Product data sheet - - - - - - 40 43 45 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 J2 Description [1] TFBGA100 P8_4 LBGA256 Pin name Reset state Table 3. I/O GPIO4[4] — General purpose digital input/output pin. I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1. - R — Function reserved.
PAGE 34
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P9_0 P9_1 P9_2 LQFP208 - - 49 T1 N6 N8 LPC185X_3X_2X_1X Product data sheet - - - - - - 59 66 70 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 L1 Description [1] TFBGA100 P8_8 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the PHY. - R — Function reserved.
PAGE 35
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued P9_4 P9_5 P9_6 LQFP208 - - 79 N10 M9 L11 LPC185X_3X_2X_1X Product data sheet - - - - 69 72 92 98 103 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 M6 Description [1] TFBGA100 P9_3 LBGA256 Pin name Reset state Table 3. I/O GPIO4[15] — General purpose digital input/output pin. O MCOA0 — Motor control PWM channel 0, output A.
PAGE 36
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued PA_1 PA_2 PA_3 LQFP208 - - 126 J14 K15 H11 LPC185X_3X_2X_1X Product data sheet - - - - - - 134 136 147 [2] [3] [3] [3] N; PU N; PU N; PU N; PU Type LQFP144 L12 Description [1] TFBGA100 PA_0 LBGA256 Pin name Reset state Table 3. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved.
PAGE 37
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued PB_0 PB_1 PB_2 LQFP208 - - 151 B15 A14 B12 LPC185X_3X_2X_1X Product data sheet - - - - - - 164 175 177 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 G13 Description [1] TFBGA100 PA_4 LBGA256 Pin name Reset state Table 3. - R — Function reserved. O CTOUT_9 — SCTimer/PWM output 9. Match output 3 of timer 3. - R — Function reserved.
PAGE 38
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued PB_4 PB_5 PB_6 LQFP208 - - 178 B11 A12 A6 LPC185X_3X_2X_1X Product data sheet - - - - - - 180 181 - [2] [2] [2] [5] N; PU N; PU N; PU N; PU Type LQFP144 A13 Description [1] TFBGA100 PB_3 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6. O LCD_VD20 — LCD data. - R — Function reserved.
PAGE 39
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued PC_1 PC_2 LQFP208 - - 7 E4 F6 LPC185X_3X_2X_1X Product data sheet - - - - 9 13 [5] [2] [2] N; PU N; PU N; PU Type LQFP144 D4 Description [1] TFBGA100 PC_0 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the PHY. - R — Function reserved.
PAGE 40
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued PC_4 LQFP208 - - 11 F4 - - 16 [5] [2] N; PU N; PU Type LQFP144 F5 Description [1] TFBGA100 PC_3 LBGA256 Pin name Reset state Table 3. I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5. - R — Function reserved. O U1_RTS — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1.
PAGE 41
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued PC_8 PC_9 PC_10 LQFP208 - - - N4 K2 M5 LPC185X_3X_2X_1X Product data sheet - - - - - - - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 G5 Description [1] TFBGA100 PC_7 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1. - R — Function reserved.
PAGE 42
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued PC_12 PC_13 PC_14 LQFP208 - - - L6 M1 N1 LPC185X_3X_2X_1X Product data sheet - - - - - - - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 L5 Description [1] TFBGA100 PC_11 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line direction.
PAGE 43
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued PD_1 PD_2 PD_3 LQFP208 - - - P1 R1 P4 LPC185X_3X_2X_1X Product data sheet - - - - - - - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 N2 Description [1] TFBGA100 PD_0 LBGA256 Pin name Reset state Table 3. - R — Function reserved. O CTOUT_15 — SCTimer/PWM output 15. Match output 3 of timer 3.
PAGE 44
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued PD_5 PD_6 PD_7 LQFP208 - - - P6 R6 T6 LPC185X_3X_2X_1X Product data sheet - - - - - - - 68 72 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 T2 Description [1] TFBGA100 PD_4 LBGA256 Pin name Reset state Table 3. - R — Function reserved. O CTOUT_8 — SCTimer/PWM output 8. Match output 0 of timer 2. I/O EMC_D18 — External memory data line 18.
PAGE 45
LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued PD_9 PD_10 PD_11 LQFP208 - - 74 T11 P11 N9 LPC185X_3X_2X_1X Product data sheet - - - - - - 84 86 88 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 P8 Description [1] TFBGA100 PD_8 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I CTIN_6 — SCTimer/PWM input 6. Capture input 1 of timer 3. I/O EMC_D22 — External memory data line 22.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued PD_13 PD_14 PD_15 LQFP208 - - 94 T14 R13 T15 LPC185X_3X_2X_1X Product data sheet - - - - - - 97 99 101 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 N11 Description [1] TFBGA100 PD_12 LBGA256 Pin name Reset state Table 3. - R — Function reserved. - R — Function reserved. O EMC_CS2 — LOW active Chip Select 2 signal. - R — Function reserved.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued PE_0 PE_1 PE_2 LQFP208 - - 104 P14 N14 M14 LPC185X_3X_2X_1X Product data sheet - - - - - - 106 112 115 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 R14 Description [1] TFBGA100 PD_16 LBGA256 Pin name Reset state Table 3. - R — Function reserved. - R — Function reserved. I/O EMC_A16 — External memory address line 16. - R — Function reserved.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued PE_4 PE_5 PE_6 LQFP208 - - 118 K13 N16 M16 LPC185X_3X_2X_1X Product data sheet - - - - - - 120 122 124 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 K12 Description [1] TFBGA100 PE_3 LBGA256 Pin name Reset state Table 3. - R — Function reserved. O CAN0_TD — CAN transmitter output. I ADCTRIG1 — ADC trigger input 1.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued PE_8 PE_9 PE_10 LQFP208 - - 149 F14 E16 E14 LPC185X_3X_2X_1X Product data sheet - - - - - - 150 152 154 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 F15 Description [1] TFBGA100 PE_7 LBGA256 Pin name Reset state Table 3. - R — Function reserved. O CTOUT_5 — SCTimer/PWM output 5. Match output 3 of timer 3. I U1_CTS — Clear to Send input for UART1.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued PE_12 PE_13 PE_14 LQFP208 - - - D15 G14 C15 LPC185X_3X_2X_1X Product data sheet - - - - - - - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP144 D16 Description [1] TFBGA100 PE_11 LBGA256 Pin name Reset state Table 3. - R — Function reserved. O CTOUT_12 — SCTimer/PWM output 12. Match output 3 of timer 3. O U1_TXD — Transmitter output for UART1.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued PF_0 PF_1 PF_2 LQFP208 - - - D12 E11 D11 LPC185X_3X_2X_1X Product data sheet - - - - - - 159 - 168 [2] [2] [2] [2] N; PU OL; PU N; PU N; PU Type LQFP144 E13 Description [1] TFBGA100 PE_15 LBGA256 Pin name Reset state Table 3. - R — Function reserved. O CTOUT_0 — SCTimer/PWM output 0. Match output 0 of timer 0.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued PF_4 PF_5 LQFP208 - - 170 D10 E9 LPC185X_3X_2X_1X Product data sheet H4 - 120 - 172 190 [2] [2] [5] N; PU OL; PU N; PU Type LQFP144 E10 Description [1] TFBGA100 PF_3 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I U3_RXD — Receiver input for USART3. I/O SSP0_MOSI — Master Out Slave in for SSP0. - R — Function reserved.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued PF_7 PF_8 LQFP208 - - 192 B7 E6 LPC185X_3X_2X_1X Product data sheet - - - - 193 - [5] [5] [5] N; PU N; PU N; PU Type LQFP144 E7 Description [1] TFBGA100 PF_6 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I/O U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. I/O SSP1_MISO — Master In Slave Out for SSP1.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued PF_10 PF_11 LQFP208 - - 203 A3 A2 - - - - 205 207 [5] [5] [5] N; PU N; PU N; PU Type LQFP144 D6 Description [1] TFBGA100 PF_9 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. O CTOUT_1 — SCTimer/PWM output 1. Match output 3 of timer 3. - R — Function reserved.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued CLK1 CLK2 CLK3 LQFP208 K3 45 62 T10 D14 P12 LPC185X_3X_2X_1X Product data sheet - K6 - - 99 - - 141 - [4] [4] [4] [4] O; PU O; PU O; PU O; PU Type LQFP144 N5 Description [1] TFBGA100 CLK0 LBGA256 Pin name Reset state Table 3. O EMC_CLK0 — SDRAM clock 0. O CLKOUT — Clock output pin. - R — Function reserved. - R — Function reserved.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued LQFP144 LQFP208 A6 28 41 Type TFBGA100 L4 Description [1] LBGA256 Pin name Reset state Table 3. Debug pins DBGEN [2] I I JTAG interface control signal. Also used for boundary scan. I; F I Test Clock for JTAG interface (default) or Serial Wire (SW) clock. TCK/SWDCLK J5 H2 27 38 [2] TRST M4 B4 29 42 [2] I; PU I Test Reset for JTAG interface.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued LQFP208 - - - Type LQFP144 C9 Description [1] TFBGA100 WAKEUP2 LBGA256 Pin name Reset state Table 3. [11] I; IA I External wake-up input; can raise an interrupt and can cause wake-up from any of the low-power modes. A pulse with a duration of at least 45 ns wakes up the part. I; IA I External wake-up input; can raise an interrupt and can cause wake-up from any of the low-power modes.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description …continued TFBGA100 LQFP144 LQFP208 Reset state VBAT B10 C5 127 184 - VDDREG F10, F9, L8, L7 E4, E5, F4 94, 131, 59, 25 135, 188, 195, 82, 33 VPP E8 - - - [12] Description Type LBGA256 Pin name [1] Table 3. - RTC power supply: 3.3 V on this pin supplies power to the RTC. - Main regulator power supply. - - OTP programming voltage. - - I/O power supply.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller [3] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V) providing digital I/O functions with TTL levels, and hysteresis; high drive strength. [4] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V) providing high-speed digital I/O functions with TTL levels and hysteresis.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7. Functional description 7.1 Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus. The I-code and D-code core buses allow for concurrent code and data accesses from different slave ports. The LPC185x/3x/2x/1x use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and other bus masters to peripherals.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Non-Maskable Interrupt (NMI). • Software interrupt generation. 7.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but can have several interrupt flags. Individual interrupt flags can also represent more than one interrupt source. 7.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.9 On-chip flash memory The LPC185x/3x/2x/1x contain up to 1 MB of dual-bank flash program memory. With dual-bank flash memory, the user code can write or erase one flash bank while reading the other flash bank without interruption. A two-port flash accelerator maximizes the flash performance. In-System Programming (ISP) and In-Application Programming (IAP) routines for programming the flash memory are provided in the Boot ROM. 7.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4. Boot mode when OTP BOOT_SRC bits are programmed Boot mode BOOT_SRC BOOT_SRC BOOT_SRC bit 3 bit 2 bit 1 BOOT_SRC Description bit 0 USB0 0 1 1 0 Boot from USB0. USB1 0 1 1 1 Boot from USB1. SPI (SSP) 1 0 0 0 Boot from SPI flash connected to the SSP0 interface on P3_3 (function SSP0_SCK), P3_6 (function SSP0_SSEL), P3_7 (function SSP0_MISO), and P3_8 (function SSP0_MOSI)[1].
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.13 One-Time Programmable (OTP) memory The OTP provides 64 bit+ 256 bit of memory for general-purpose use. 7.14 General-Purpose I/O (GPIO) The LPC185x/3x/2x/1x provides 8 GPIO ports with up to 31 GPIO pins each. Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • • • • • 7.15.1.1 Clock selection Inputs Events Outputs Interrupts Features • • • • • Two 16-bit counters or one 32-bit counter. Counters clocked by bus clock or selected input. Up counters or up-down counters. State variable allows sequencing across multiple counter cycles.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. • Hardware DMA channel priority. • AHB slave DMA programming interface. The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface. • Two AHB bus masters for transferring data.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.15.4 SD/MMC card interface The SD/MMC card interface supports the following modes: • • • • Secure Digital memory (SD version 3.0) Secure Digital I/O (SDIO version 2.0) Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1) Multimedia Cards (MMC version 4.4) 7.15.5 External Memory Controller (EMC) Remark: The EMC is available on all LPC185x/3x/2x/1x parts.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • • • • Read and write buffers to reduce latency and to improve performance. 8/16/32 data and 24 address lines-wide static memory support. 16-bit and 32-bit wide chip select SDRAM memory support.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.15.7 High-speed USB Host/Device interface with ULPI (USB1) Remark: USB1 is available on the following parts: LPC185x and LPC183x. USB1 is not available on the LPC182x and LPC181x parts. The USB1 interface can operate as a full-speed USB host/device interface or can connect to an external ULPI PHY for High-speed operation. 7.15.7.1 Features • • • • Complies with Universal Serial Bus specification 2.0.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • • • • • • • • • • • 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support. 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN. 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT. 16 bpp true-color non-palettized for color STN and TFT. 24 bpp true-color non-palettized for color TFT. Programmable timing for different display panels.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.16.1.1 Features • • • • • Maximum UART data bit rate of 8 MBit/s. 16 B Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.16.3.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller The I2S-bus provides a standard communication interface for digital audio applications. The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S-bus connection has one master, which is always the master, and one slave. The I2S-bus interface provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 7.16.5.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.17 Counter/timers and motor control 7.17.1 General purpose 32-bit timers/external event counter Remark: The LPC185x/3x/2x/1x include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • • • • • • • • • Increments/decrements depending on direction. Programmable for 2 or 4 position counting. Velocity capture using built-in timer. Velocity compare function with “less than” interrupt. Uses 32-bit registers for position and velocity. Three position-compare registers with interrupts. Index counter for revolution counting. Index compare register with interrupts.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in multiples of Tcy(WDCLK)  4. • The Watchdog Clock (WDCLK) uses the IRC as the clock source. 7.18 Analog peripherals 7.18.1 Analog-to-Digital Converter Remark: The LPC185x/3x/2x/1x contain two 10-bit ADCs. All input channels are shared between ADC0 and ADC1. 7.18.1.1 Features • • • • • • • 10-bit successive approximation analog to digital converter.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • • • • • Dedicated battery power supply pin. RTC power supply is isolated from the rest of the chip. Calibration counter allows adjustment to better than 1 sec/day with 1 sec resolution. Periodic interrupts can be generated from increments of any field of the time registers. Alarm interrupt can be generated for a specific date/time. 7.19.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Timer/USART inputs • Enabling the USB controllers In addition, the CREG block contains the part identification and part configuration information. 7.20.2 System Control Unit (SCU) The system control unit determines the function and electrical mode of the digital pins. By default function 0 is selected for all pins with pull-up enabled.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller output frequency. The output frequency can be set as a multiple of the sampling frequency fs to 32fs, 64fs, 128  fs, 256  fs, 384  fs, 512  fs and the sampling frequency fs can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48, 96,192) kHz. Many other frequencies are possible as well using the integrated fractional divider. 7.20.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC18xx to I/O pads VDDIO to core VSS REGULATOR to memories, peripherals, oscillators, PLLs VDDREG MAIN POWER DOMAIN ULTRA LOW-POWER REGULATOR VBAT to RTC domain peripherals RESET WAKEUP0/1/2/3 RESET/WAKE-UP CONTROL to RTC I/O pads (Vps) BACKUP REGISTERS RTCX1 32 kHz OSCILLATOR RTCX2 ALARM REAL-TIME CLOCK ALWAYS-ON/RTC POWER DOMAIN DAC VDDA VSSA ADC ADC POWER DOMAIN OTP VPP OTP POWER DOMAIN USB0_VDDA3V3_DRIVER US
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller There are three levels of the Code Read Protection: • In level CRP1, access to the chip via the JTAG is disabled. Partial flash updates are allowed (excluding flash sector 0) using a limited set of the ISP commands. This level is useful when CRP is required and flash field updates are needed. CRP1 does prevent the user code from erasing all sectors. • In level CRP2, access to the chip via the JTAG is disabled.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8. Limiting values Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(REG)(3V3) regulator supply voltage (3.3 V) on pin VDDREG 0.5 3.6 V VDD(IO) input/output supply voltage on pin VDDIO 0.5 3.6 V VDDA(3V3) analog supply voltage (3.3 V) on pin VDDA 0.5 3.6 V VBAT battery supply voltage on pin VBAT 0.5 3.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 9. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb +  P D  R th  j – a   (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD(REG)(3V3) and VDD(REG)(3V3).
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10. Static characteristics Table 11. Static characteristics Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Min Typ[1] Max Unit 2.2 - 3.6 V 2.2 - 3.6 V on pin VDDA 2.2 - 3.6 V on pins USB0_VDDA3V3_ DRIVER and USB0_VDDA3V3 3.0 3.3 3.6 V Conditions Supply pins VDD(IO) input/output supply voltage VDD(REG)(3V3) regulator supply voltage (3.3 V) VDDA(3V3) analog supply voltage (3.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IDD(IO) I/O supply current deep sleep mode - < 0.1 - A power-down mode - < 0.1 - A - < 0.1 - A - 0.4 - deep power-down mode IDDA Analog supply current on pin VDDA; [9] A deep sleep mode power-down mode [9] - 0.4 - deep power-down mode [9] - 0.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IOL LOW-level output current VOL = 0.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Min Typ[1] Max Unit VI = VDD(IO); on-chip pull-down resistor disabled - 3 - nA VI = 5 V; Tamb = 25 °C - 0.6 - nA VI = 5 V; Tamb = 105 °C - 65 - nA Conditions I/O pins - high drive strength: standard drive mode ILH HIGH-level leakage current IOH HIGH-level output current VOH = VDD(IO)  0.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Min Typ[1] Max Unit VI = VDD(IO); on-chip pull-down resistor disabled - 3 - nA VI = 5 V; Tamb = 25 °C - 0.6 - nA VI = 5 V; Tamb = 105 °C - 63 - nA Conditions I/O pins - high drive strength: ultra-high drive mode ILH HIGH-level leakage current IOH HIGH-level output current VOH = VDD(IO)  0.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IOL LOW-level output current VOL = 0.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions [17] Min Typ[1] Max Unit - - 5.25 V VBUS bus supply voltage VDI differential input sensitivity voltage (D+)  (D) 0.2 - - V VCM differential common mode voltage range includes VDI range 0.8 - 2.5 V Vth(rs)se single-ended receiver switching threshold voltage 0.8 - 2.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10.1 Power consumption aaa-013045 100 IDD(REG)(3V3) (mA) 80 180 MHz 60 120 MHz 40 60 MHz 20 12 MHz 0 2.2 2.4 2.6 2.8 3 3.2 3.4 VDD(REG)(3V3) (V) 3.6 Conditions: Tamb = 25 C; executing code while (1){} from SRAM; system PLL enabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled. Fig 10.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller aaa-013046 100 IDD(REG)(3V3) (mA) +105 °C +90 °C +25 °C 0 °C -40 °C 80 60 40 20 0 12 36 60 84 108 132 156 frequency (MHz) 180 Conditions: active mode entered executing code while (1){} from SRAM; VDD(REG)(3V3) = 3.3 V; system PLL enabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled. Fig 12.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aah410 1.6 IDD(REG)(3V3) (μA) (mA) 002aah412 300 IDD(REG)(3V3) (μA)(μA) 240 1.2 180 0.8 120 0.4 60 0 -40 0 40 80 temperature (°C) 0 -40 120 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V. 40 80 temperature (°C) 120 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V. Fig 14. Typical supply current versus temperature in Deep-sleep mode Fig 15.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aah379 100 IBAT (μA) 80 60 40 20 0 -0.4 -0.2 0 0.2 0.4 VBAT - VDD(REG)(3V3) (V) 0.6 Conditions: VDD(REG)(3V3) = 3.0 V; VBAT = 2.6 V to 3.6 V; CCLK = 12 MHz. Remark: The recommended operating condition for the battery supply is VDD(REG)(3V3) > VBAT + 0.2 V. Fig 18. Typical battery supply current in Active mode 10.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 12. Peripheral power consumption Peripheral LCD LPC185X_3X_2X_1X Product data sheet Branch clock CLK_M3_LCD IDD(REG)(3V3) in mA Branch clock frequency = 48 MHz Branch clock frequency = 96 MHz 0.91 1.82 ETHERNET CLK_M3_ETHERNET 1.06 2.15 UART0 CLK_M3_UART0, CLK_APB0_UART0 0.24 0.43 UART1 CLK_M3_UART1, CLK_APB0_UART1 0.24 0.43 UART2 CLK_M3_UART2, CLK_APB2_UART2 0.26 0.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10.3 Electrical pin characteristics 002aah358 15 -40 °C +25 °C +85 °C +105 °C IOL (mA) 12 002aah359 3.6 VOH (V) 3.2 9 -40 °C +25 °C +85 °C +105 °C 2.8 6 2.4 3 0 2 0 0.1 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V. Product data sheet 6 12 18 24 30 IOH (mA) 36 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V. Fig 19.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aah360 15 -40 °C +25 °C +85 °C +105 °C IOL (mA) 12 002aah361 25 -40 °C +25 °C +85 °C +105 °C IOL (mA) 20 9 15 6 10 3 5 0 0 0 0.1 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; normal-drive; EHD = 0x0. 0 -40 °C +25 °C +85 °C +105 °C 32 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; medium-drive; EHD = 0x1. 002aah362 40 IOL (mA) 0.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aah364 3.6 VOH (V) 002aah367 3.6 VOH (V) -40 °C +25 °C +85 °C +105 °C 3.2 2.8 -40 °C +25 °C +85 °C +105 °C 3.2 2.8 2.4 2.4 2 2 0 4 8 12 16 20 IOH (mA) 24 0 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; normal-drive; EHD = 0x0. 16 24 32 40 IOH (mA) 48 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; medium-drive; EHD = 0x1. 002aah368 3.6 VOH (V) 8 002aah369 3.6 VOH (V) -40 °C +25 °C +85 °C +105 °C 3.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aah422 20 IIpu pu (μA) 0 +105 °C C +25 °C C -40 °C C -20 -40 -60 -80 0 1 2 3 4 VI (V) 5 Conditions: VDD(IO) = 3.3 V. Simulated data over process and temperature. Fig 23. Pull-up current Ipu versus input voltage VI 002aah418 120 IIpd pd (μA) -40 °C C +25 °C C +105 °C C 90 60 30 0 0 1 2 3 4 VI (V) 5 Conditions: VDD(IO) = 3.3 V. Simulated data over process and temperature. Fig 24.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10.4 BOD and band gap static characteristics Table 13. BOD static characteristics[1] Tamb = 25 C; simulated values for nominal processing. Symbol Parameter Conditions Vth threshold voltage interrupt level 0 Min Typ Max Unit assertion - 2.25 - V de-assertion - 2.33 - V assertion - 2.35 - V de-assertion - 2.43 - V assertion - 2.95 - V de-assertion - 3.03 - V assertion - 3.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11. Dynamic characteristics 11.1 Flash/EEPROM memory Table 14. Flash characteristics Tamb = 40 C to +105 C, unless otherwise specified. VDD(REG)(3V3) = 2,2 V to 3.6 V for read operations; VDD(REG)(3V3) = 2.7 V to 3.6 V for erase/program operations.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.2 Wake-up times Table 16. Dynamic characteristic: Wake-up from Deep-sleep, Power-down, and Deep power-down modes Tamb = 40 C to +105 C Symbol Parameter twake Conditions Typ[1] Min Max Unit 3  Tcy(clk) 5  Tcy(clk) - ns from Deep-sleep and Power-down mode 12 51 - s from Deep power-down mode - 200 - μs after reset - 200 - μs [2] wake-up time from Sleep mode [1] Typical ratings are not guaranteed.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.4 Crystal oscillator Table 18. Dynamic characteristic: oscillator Tamb = 40 C to +105 C; VDD(IO) over specified ranges; 2.2 V  VDD(REG)(3V3)  3.6 V.[1] Symbol Parameter Conditions Low-frequency mode (1-20 tjit(per) Typ[2] Max Unit MHz)[5] period jitter time High-frequency mode (20 - 25 tjit(per) Min [3][4] 5 MHz crystal - 13.2 - ps 10 MHz crystal - 6.6 - ps 15 MHz crystal - 4.8 - ps - 4.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.7 I2C-bus Table 21. Dynamic characteristic: I2C-bus pins Tamb = 40 C to +105 C; 2.2 V  VDD(REG)(3V3)  3.6 V.[1] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz [3][4][5][6] fall time tf Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz of both SDA and SCL signals - 300 ns Fast-mode 20 + 0.1  Cb 300 ns Fast-mode Plus - 120 ns Standard-mode 4.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller tf SDA tSU;DAT 70 % 30 % 70 % 30 % tHD;DAT tf 70 % 30 % SCL tVD;DAT tHIGH 70 % 30 % 70 % 30 % 70 % 30 % tLOW 1 / fSCL S 002aaf425 Fig 26. I2C-bus pins clock timing 11.8 I2S-bus interface Table 22. Dynamic characteristics: I2S-bus interface pins Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Conditions and data refer to I2S0 and I2S1 pins. Simulated values.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Tcy(clk) tf tr I2Sx_TX_SCK tWH tWL I2Sx_TX_SDA tv(Q) I2Sx_TX_WS 002aag497 tv(Q) Fig 27. I2S-bus timing (transmit) Tcy(clk) tf tr I2Sx_RX_SCK tWH tWL I2Sx_RX_SDA tsu(D) th(D) I2Sx_RX_WS tsu(D) 002aag498 tsu(D) Fig 28. I2S-bus timing (receive) 11.9 USART interface Table 23. Dynamic characteristics: USART interface Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.10 SSP interface Table 24. Dynamic characteristics: SSP pins in SPI mode Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. Simulated values. Symbol Tcy(clk) Parameter clock cycle time Conditions Min Typ Max Unit - 40 - ns when only transmitting - 20 - ns full-duplex mode [1] SSP master tDS data set-up time in SPI mode 13.3 - - ns tDH data hold time in SPI mode 3.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) th(Q) DATA VALID MOSI DATA VALID tDS DATA VALID MISO DATA VALID tv(Q) MOSI th(Q) DATA VALID DATA VALID tDH tDS MISO CPHA = 1 tDH DATA VALID CPHA = 0 DATA VALID 002aae829 Fig 29.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.11 External memory interface Table 25. Dynamic characteristics: Static external memory interface CL = 22 pF for EMC_Dn CL = 20 pF for all others; Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; values guaranteed by design. Timing parameters are given for single memory access cycles.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 25. Dynamic characteristics: Static external memory interface …continued CL = 22 pF for EMC_Dn CL = 20 pF for all others; Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; values guaranteed by design. Timing parameters are given for single memory access cycles. In a normal read operation, the EMC changes the address while CS is asserted which results in multiple memory accesses.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller EMC_An tCSLAV tCSLAV tOEHANV tCSHEOW EMC_CSn tCSLOEL tOELOEH EMC_OE tCSLBLSL tCSHOEH tCSLBLSL EMC_BLSn tCSHBLSH tCSLWEL tWELWEH tWEHEOW EMC_WE tBLSHDNV tam tCSHEOR th(D) tCSLSOR tCSLDV tWEHDNV EMC_Dn SOR EOR EOW 002aag700 Fig 32. External static memory read/write access (PB = 1) LPC185X_3X_2X_1X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 26. Dynamic characteristics: Dynamic external memory interface Simulated data over temperature and process range; CL = 10 pF for EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE, EMC_An; CL = 9 pF for EMC_Dn; CL = 5 pF for EMC_DQMOUTn, EMC_CLKn, EMC_CKEOUTn; Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; VDD(IO) =3.3 V  10 %; RD = 1 (see LPC18xx User manual); EMC_CLKn delays CLK0_DELAY = CLK1_DELAY = CLK2_DELAY = CLK3_DELAY = 0.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller EMC_CLKn delay > 0 EMC_CLKn delay td; programmable CLKn_DELAY Tcy(clk) EMC_CLKn delay = 0 td(xV) - td EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE, EMC_CKEOUTn, EMC_A[22:0], EMC_DQMOUTn td(xV) th(x) - td th(x) td(QV) - td td(QV) th(Q) - td th(Q) EMC_D[31:0] write tsu(D) th(D) EMC_D[31:0] read; delay > 0 tsu(D) th(D) EMC_D[31:0] read; delay = 0 002aag703 For the programmable EMC_CLK[3:0] clock delays CLKn_DELAY, see Table 27.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.12 USB interface Table 28. Dynamic characteristics: USB0 and USB1 pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD(IO), unless otherwise specified; 3.0 V  VDD(IO)  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 % to 90 % 8.5 - 13.8 ns tf fall time 10 % to 90 % 7.7 - 13.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Static characteristics: USB0 PHY pins[1] Table 29. Symbol Parameter Conditions Min Typ Max Unit - 68 - mW total supply current - 18 - mA during transmit - 31 - mA during receive - 14 - mA with driver tri-stated - 14 - mA - 7 - mA - 15 - mW High-speed mode Pcons [2] power consumption IDDA(3V3) analog supply current (3.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 30. Dynamic characteristics: Ethernet Tamb = 40 C to 105 C, 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. Values guaranteed by design.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.14 SD/MMC Table 31. Dynamic characteristics: SD/MMC Tamb = 40 C to 105 C, 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V, CL = 20 pF. Simulated values.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.16 SPIFI Table 33. Dynamic characteristics: SPIFI Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. CL = 10 pF. Simulated values. Symbol Parameter Min Max Unit Tcy(clk) clock cycle time 9.6 - ns tDS data set-up time 3.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12. ADC/DAC electrical characteristics Table 34. ADC characteristics VDDA(3V3) over specified ranges; Tamb = 40 C to +105 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VIA analog input voltage 0 - VDDA(3V3) V Cia analog input capacitance - - 2 pF ED differential linearity error - 0.8 - LSB - 1.0 - LSB - 0.8 - LSB - 1.5 - LSB - 0.15 - LSB - 0.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = VDDA(3V3) − VSSA 1024 002aaf959 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Rvsi LPC18xx 2 kΩ (analog pin) 2.2 kΩ (multiplexed pin) ADC0_n/ADC1_n Rs ADC COMPARATOR Cia = 2 pF VEXT VSS 002aag697 Rs < 1/((7  fclk(ADC)  Cia)  2 k Fig 39. ADC interface to pins Table 35. DAC characteristics VDDA(3V3) over specified ranges; Tamb = 40 C to +105 C; unless otherwise specified Symbol Parameter Conditions ED differential linearity error 2.7 V  VDDA(3V3)  3.6 V [1] 2.2 V  VDDA(3V3) < 2.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 13. Application information 13.1 LCD panel signal usage Table 36.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 37.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 38.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 39. Recommended values for CX1/X2 in oscillation mode (crystal and external components parameters) low frequency mode Fundamental oscillation frequency Maximum crystal series resistance RS External load capacitors CX1, CX2 12 MHz < 160  18 pF, 18 pF < 160  39 pF, 39 pF 16 MHz < 120  18 pF, 18 pF < 80  33 pF, 33 pF < 100  18 pF, 18 pF < 80  33 pF, 33 pF 20 MHz Table 40.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 13.3 RTC oscillator In the RTC oscillator circuit, only the crystal (XTAL) and the capacitances CRTCX1 and CRTCX2 need to be connected externally. Typical capacitance values for CRTCX1 and CRTCX2 are CRTCX1/2 = 20 (typical)  4 pF. An external clock can be connected to RTCX1 if RTCX2 is left open. The recommended amplitude of the clock signal is Vi(RMS) = 100 mV to 200 mV with a coupling capacitance of 5 pF to 10 pF.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller VDDIO ESD enable output driver data output from core PIN slew rate bit EHS input buffer enable bit EZI data input to core glitch filter filter select bit ZIF pull-up enable bit EPUN ESD pull-down enable bit EPD analog I/O VSSIO 002aah028 The glitch filter rejects pulses of typical 12 ns width. Fig 43. Standard I/O pin configuration with analog input 13.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller On the LPC185x/3x/2x/1x, USBn_VBUS pins are 5 V tolerant only when VDDIO is applied and at operating voltage level. Therefore, if the USBn_VBUS function is connected to the USB connector and the device is self-powered, the USBn_VBUS pins must be protected for situations when VDDIO = 0 V. If VDDIO is always at operating level while VBUS = 5 V, the USBn_VBUS pin can be connected directly to the VBUS pin on the USB connector.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC18xx VDDREG REGULATOR USBn_VBUS VBUS USB-B connector USB aaa-013016 Fig 46. USB interface on a bus-powered device Remark: If the VBUS function of the USB1 interface is not connected, configure the pin function for GPIO using the function control bits in the SYSCON block. VDDIO R1 LPC18xx T2 R2 T1 R3 USBn_VBUS VBUS USB-B connector USB aaa-013017 Fig 47.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 14.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm B D SOT926-1 A ball A1 index area A2 E A A1 detail X e1 e ∅v ∅w b 1/2 e C M M C A B C y y1 C K J e H G F e2 E D 1/2 e C B A ball A1 index area 1 2 3 4 5 6 7 8 9 10 X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 b D E e e1 e2 v w y y1 mm 1.2 0.4 0.3 0.8 0.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1 c y X A 105 156 157 104 ZE e E HE (A 3) A A2 A1 wM θ Lp bp L detail X pin 1 index 208 53 1 52 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 28.1 27.9 28.1 27.9 0.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1 c y X A 73 72 108 109 ZE e E HE A A2 (A 3) A1 θ wM Lp bp L pin 1 index detail X 37 144 1 36 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 20.1 19.9 0.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 15. Soldering Footprint information for reflow soldering of LBGA256 package SOT740-2 Hx P P Hy see detail X Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste SL SP occupied area SR solder resist detail X DIMENSIONS in mm P SL SP SR 1.00 0.450 0.450 0.600 Hx Hy 17.500 17.500 sot740-2_fr Fig 52.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of TFBGA100 package SOT926-1 Hx P P Hy see detail X Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste SL SP occupied area SR solder resist detail X DIMENSIONS in mm P SL SP SR Hx Hy 0.80 0.330 0.400 0.480 9.400 9.400 sot926-1_fr Fig 53.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of LQFP208 package SOT459-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 31.300 31.300 28.300 28.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 28.500 28.500 31.550 31.550 sot459-1_fr Fig 54.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of LQFP144 package SOT486-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 23.300 23.300 20.300 20.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 20.500 20.500 23.550 23.550 sot486-1_fr Fig 55.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 16. Abbreviations Table 41.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 41. Abbreviations …continued Acronym Description USART Universal Synchronous Asynchronous Receiver/Transmitter USB Universal Serial Bus UTMI USB 2.0 Transceiver Macrocell Interface 17. References LPC185X_3X_2X_1X Product data sheet [1] LPC18xx User manual UM10430: http://www.nxp.com/documents/user_manual/UM10430.pdf [2] LPC18xx Errata sheet: http://www.nxp.com/documents/errata_sheet/ES_LPC18XX.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 18. Revision history Table 42. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC185X_3X_2X_1X v.4.1 20140506 - Modifications: • • Product data sheet LPC185X_3X_2X_1X v.4 Parameter tret (retention time) for EEPROM updated in Table 15. Parameter VDDA(3V3) added for pins USB0_VDDA3V3_DRIVER and USB0_VDDA3V3 in Table 11. • • • • • Parameter name IDD(ADC) changed to IDDA in Table 11.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 42. Revision history …continued Document ID Modifications: LPC1857_53 v.3.2 Release date Data sheet status Change notice Supersedes • • • SPIFI dynamic characteristics added in Section 11.16. • SCT dither engine added and SCT bi-directional event enable features added. See Section 7.15.1. • • SPIFI maximum data rate changed to 52 MB per second. • • • Table 14 “Band gap characteristics” added.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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LPC185x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 21. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.5.1 7.5.2 7.6 7.7 7.7.1 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.14.1 7.15 7.15.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Ordering options . . . . . . . .
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NXP Semiconductors LPC185x/3x/2x/1x 32-bit ARM Cortex-M3 microcontroller 7.21 8 9 10 10.1 10.2 10.3 10.4 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 11.14 11.15 11.16 12 13 13.1 13.2 13.3 13.4 13.5 13.6 13.7 14 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 Emulation and debugging . . . . . . . . . . . . . . . . 84 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 85 Thermal characteristics . . . . . . . . . . . . . . . . . 86 Static characteristics. . . . . . . . . .