Datasheet

LPC185X_3X_2X_1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.1 — 6 May 2014 110 of 148
NXP Semiconductors
LPC185x/3x/2x/1x
32-bit ARM Cortex-M3 microcontroller
11.10 SSP interface
[1] T
cy(clk)
= (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f
main
. The clock cycle time derived from the SPI bit rate T
cy(clk)
is a function of the
main clock frequency f
main
, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
[2] T
cy(clk)
= 12  T
cy(PCLK)
.
Table 24. Dynamic characteristics: SSP pins in SPI mode
T
amb
=  40  C to 105  C; 2.2 V  V
DD(REG)(3V3)
 3.6 V; 2.7 V  V
DD(IO)
 3.6 V. Simulated values.
Symbol Parameter Conditions Min Typ Max Unit
T
cy(clk)
clock cycle time full-duplex mode
[1]
-40-ns
when only
transmitting
-20-ns
SSP master
t
DS
data set-up time in SPI mode 13.3 - - ns
t
DH
data hold time in SPI mode 3.5 - - ns
t
v(Q)
data output valid time in SPI mode - - 6.0 ns
t
h(Q)
data output hold time in SPI mode - - 0 ns
SSP slave
T
cy(PCLK)
PCLK cycle time 10 ns
T
cy(clk)
clock cycle time
[2]
120 - - ns
t
DS
data set-up time in SPI mode - 10.5 - ns
t
DH
data hold time in SPI mode - 1 - ns
t
v(Q)
data output valid time in SPI mode - 4.0 - ns
t
h(Q)
data output hold time in SPI mode - 0.2 - ns