Datasheet

LPC185X_3X_2X_1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.1 — 6 May 2014 116 of 148
NXP Semiconductors
LPC185x/3x/2x/1x
32-bit ARM Cortex-M3 microcontroller
For the programmable EMC_CLK[3:0] clock delays CLKn_DELAY, see Table 27.
Remark: For SDRAM operation, set CLK0_DELAY = CLK1_DELAY = CLK2_DELAY = CLK3_DELAY in the EMCDELAYCLK
register.
Fig 33. SDRAM timing
002aag703
T
cy(clk)
EMC_CLKn
delay = 0
EMC_CLKn
delay > 0
EMC_DYCSn,
EMC_RAS,
EMC_CAS,
EMC_WE,
EMC_CKEOUTn,
EMC_A[22:0],
EMC_DQMOUTn
t
h(Q)
t
h(Q)
- t
d
t
h(D)
t
su(D)
t
h(D)
t
su(D)
EMC_D[31:0]
write
EMC_D[31:0]
read; delay = 0
EMC_D[31:0]
read; delay > 0
t
h(x)
- t
d
t
d(xV)
- t
d
t
d(QV)
- t
d
t
d(QV)
t
h(x)
t
d(xV)
EMC_CLKn delay t
d
; programmable CLKn_DELAY