Datasheet

LPC185X_3X_2X_1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.1 — 6 May 2014 56 of 148
NXP Semiconductors
LPC185x/3x/2x/1x
32-bit ARM Cortex-M3 microcontroller
Debug pins
DBGEN L4 A6 28 41
[2]
I I JTAG interface control signal. Also used for boundary scan.
TCK/SWDCLK J5 H2 27 38
[2]
I; F I Test Clock for JTAG interface (default) or Serial Wire (SW)
clock.
TRST
M4 B4 29 42
[2]
I; PU I Test Reset for JTAG interface.
TMS/SWDIO K6 C4 30 44
[2]
I; PU I Test Mode Select for JTAG interface (default) or SW debug
data input/output.
TDO/SWO K5 H3 31 46
[2]
O O Test Data Out for JTAG interface (default) or SW trace output.
TDI J4 G3 26 35
[2]
I; PU I Test Data In for JTAG interface.
USB0 pins
USB0_DP F2 E1 18 26
[6]
- I/O USB0 bidirectional D+ line. Do not add an external series
resistor.
USB0_DM G2 E2 20 28
[6]
- I/O USB0 bidirectional D line. Do not add an external series
resistor.
USB0_VBUS F1 E3 21 29
[6]
[7]
- I/O VBUS pin (power on USB cable). This pin includes an internal
pull-down resistor of 70 k (typical)  30 k.
USB0_ID H2 F1 22 30
[8]
- I Indicates to the transceiver whether connected as an A-device
(USB0_ID LOW) or B-device (USB0_ID HIGH). For use with
OTG, this pin has an internal pull-up resistor.
USB0_RREF H1 F3 24 32
[8]
-12.0 k (accuracy 1 %) on-board resistor to ground for current
reference.
USB1 pins
USB1_DP F12 E9 89 129
[9]
- I/O USB1 bidirectional D+ line. Add an external series resistor of
33  +/- 2 %.
USB1_DM G12 E10 90 130
[9]
- I/O USB1 bidirectional D line. Add an external series resistor of
33  +/- 2 %.
I
2
C-bus pins
I2C0_SCL L15 D6 92 132
[10]
I; F I/O I
2
C clock input/output. Open-drain output (for I
2
C-bus
compliance).
I2C0_SDA L16 E6 93 133
[10]
I; F I/O I
2
C data input/output. Open-drain output (for I
2
C-bus
compliance).
Reset and wake-up pins
RESET
D9 B6 128 185
[11]
I; IA I External reset input: A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default
states, and processor execution to begin at address 0.
WAKEUP0 A9 A4 130 187
[11]
I; IA I External wake-up input; can raise an interrupt and can cause
wake-up from any of the low-power modes. A pulse with a
duration of at least 45 ns wakes up the part.
Input 0 of the event monitor.
WAKEUP1 A10 - - -
[11]
I; IA I External wake-up input; can raise an interrupt and can cause
wake-up from any of the low-power modes. A pulse with a
duration of at least 45 ns wakes up the part.
Input 1 of the event monitor.
Table 3. Pin description
…continued
Pin name
LBGA256 TFBGA100 LQFP144 LQFP208 Reset state [1] Type
Description