Datasheet

Product data sheet Rev. 4.1 — 6 May 2014 59 of 148

NXP Semiconductors

LPC185x/3x/2x/1x

32-bit ARM Cortex-M3 microcontroller

[3] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V) providing digital I/O

functions with TTL levels, and hysteresis; high drive strength.

[4] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V) providing high-speed

digital I/O functions with TTL levels and hysteresis.

[5] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output (5 V tolerant if VDDIO present;

if VDDIO not present, do not exceed 3.6 V). When configured as an ADC input or DAC output, the pin is not 5 V tolerant. For analog

functionality, disable the digital section of the pad by setting the pin to an input function and by disabling the pull-up resistor through the

corresponding SFSP register.

[6] 5 V tolerant transparent analog pad.

[7] For maximum load C

= 6.5 F and maximum resistance R

= 80 k, the VBUS signal takes about 2 s to fall from VBUS = 5 V to VBUS

= 0.2 V when it is no longer driven.

[8] Transparent analog pad. Not 5 V tolerant.

[9] Pad provides USB functions; It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode

only).

[10] Open-drain 5 V tolerant digital I/O pad, compatible with I

C-bus Fast Mode Plus specification. This pad requires an external pull-up to

provide output functionality. When power is switched off, this pin connected to the I

C-bus is floating and does not disturb the I

C lines.

[11] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output with weak pull-up resistor and hysteresis.

[12] On the LQFP208 package, VPP is internally connected to VDDIO.

[13] On the LQFP208 package, VSSIO and VSS are connected to a common ground plane.