Datasheet

LPC185X_3X_2X_1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.1 — 6 May 2014 6 of 148
NXP Semiconductors
LPC185x/3x/2x/1x
32-bit ARM Cortex-M3 microcontroller
5. Block diagram
(1) Not available on all parts. See Tab le 2 .
Fig 1. LPC185x/3x/2x/1x block diagram
ARM
CORTEX-M3
TEST/DEBUG
INTERFACE
I-code bus D-code bus system bus
SWD/TRACE PORT/JTAG
DMA
ETHERNET
(1)
10/100
MAC
IEEE 1588
USB1
(1)
HOST/
DEVICE
HIGH-
SPEED
USB0
(1)
HOST/
DEVICE/
OTG
LCD
(1)
SD/
MMC
EMC
HIGH-SPEED PHY
32 kB AHB SRAM
16 kB +
16 kB AHB SRAM
SPIFI
HS GPIO
SCT
64 kB ROM
AHB MULTILAYER MATRIX
LPC185x/3x/2x/1x
32 kB LOCAL SRAM
40 kB LOCAL SRAM
002aah225
slaves
masters
WWDT
USART0
UART1
SSP0
I
2
C0
C_CAN1
I
2
S0
I
2
S1
MOTOR
CONTROL
PWM
(1)
TIMER3
TIMER2
USART2
USART3
SSP1
RI TIMER
QEI
(1)
GIMA
BRIDGE 0 BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE
10-bit ADC0
10-bit ADC1
C_CAN0
I
2
C1
10-bit DAC
BRIDGE
RGU
CCU2
CGU
CCU1
ALARM TIMER
CONFIGURATION
REGISTERS
OTP MEMORY
EVENT ROUTER
POWER MODE CONTROL
12 MHz IRC
EVENT MONITOR
RTC POWER DOMAIN
BACKUP REGISTERS
RTC OSC
RTC
slaves
= connected to DMA
TIMER0
TIMER1
SCU
GPIO PIN
INTERRUPTS
GPIO GROUP0
INTERRUPT
GPIO GROUP1
INTERRUPT
512/256 kB FLASH A
512/256 kB FLASH B
16 kB EEPROM
ETM