Datasheet

Product data sheet Rev. 4.1 — 6 May 2014 60 of 148

NXP Semiconductors

LPC185x/3x/2x/1x

32-bit ARM Cortex-M3 microcontroller

7. Functional description

7.1 Architectural overview

The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and

the D-code bus. The I-code and D-code core buses allow for concurrent code and data

accesses from different slave ports.

The LPC185x/3x/2x/1x use a multi-layer AHB matrix to connect the ARM Cortex-M3

buses and other bus masters to peripherals. Flexible connections allow different bus

masters to access peripherals that are on different slave ports of the matrix

simultaneously.

7.2 ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high

performance and low-power consumption. The ARM Cortex-M3 offers many new

features, including a Thumb-2 instruction set, low interrupt latency, hardware division,

hardware single-cycle multiply, interruptable/continuable multiple load and store

instructions, automatic state save and restore for interrupts, tightly integrated interrupt

controller with wake-up interrupt controller, and multiple core buses capable of

simultaneous accesses.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical

Reference Manual.

7.3 System Tick timer (SysTick)

The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a 10 ms interval.