Datasheet

LPC185X_3X_2X_1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.1 — 6 May 2014 61 of 148
NXP Semiconductors
LPC185x/3x/2x/1x
32-bit ARM Cortex-M3 microcontroller
7.4 AHB multilayer matrix
7.5 Nested Vectored Interrupt Controller (NVIC)
The NVIC is part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt
latency and efficient processing of late arriving interrupts.
7.5.1 Features
• Controls system exceptions and peripheral interrupts.
• On the LPC185x/3x/2x/1x, the NVIC supports 53 vectored interrupts.
• Eight programmable interrupt priority levels, with hardware priority level masking.
• Relocatable vector table.
Fig 6. AHB multilayer matrix master and slave connections
ARM
CORTEX-M3
TEST/DEBUG
INTERFACE
DMA ETHERNET USB1USB0 LCD
SD/
MMC
EXTERNAL
MEMORY
CONTROLLER
AHB REGISTER
INTERFACES,
APB, RTC DOMAIN
PERIPHERALS
32 kB AHB SRAM
16 kB AHB SRAM
16 kB AHB SRAM
slaves
64 kB ROM
32 kB LOCAL SRAM
40 kB LOCAL SRAM
System
bus
I-code
bus
D-code
bus
masters
01
256/512 kB FLASH A
256/512 kB FLASH B
16 kB EEPROM
SPIFI
AHB MULTILAYER MATRIX
= master-slave connection
002aag544
HIGH-SPEED PHY