Datasheet

Product data sheet Rev. 4.1 — 6 May 2014 62 of 148

NXP Semiconductors

LPC185x/3x/2x/1x

32-bit ARM Cortex-M3 microcontroller

• Non-Maskable Interrupt (NMI).

• Software interrupt generation.

7.5.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but can have several

interrupt flags. Individual interrupt flags can also represent more than one interrupt

source.

7.6 Event router

The event router combines various internal signals, interrupts, and the external interrupt

pins (WAKEUP[3:0]) to create an interrupt in the NVIC, if enabled. In addition, the event

router creates a wake-up signal to the ARM core and the CCU for waking up from Sleep,

Deep-sleep, Power-down, and Deep power-down modes. Individual events can be

configured as edge or level sensitive and can be enabled or disabled in the event router.

The event router can be battery powered.

The following events if enabled in the event router can create a wake-up signal from

sleep, deep-sleep, power-down, and deep power-down modes and/or create an interrupt:

• External pins WAKEUP0/1/2/3 and RESET

• Alarm timer, RTC (32 kHz oscillator running)

The following events if enabled in the event router can create a wake-up signal from sleep

mode only and/or create an interrupt:

• WWDT, BOD interrupts

• C_CAN0/1 and QEI interrupts

• Ethernet, USB0, USB1 signals

• Selected outputs of combined timers (SCTimer/PWM and timer0/1/3)

Remark: Any interrupt can wake up the ARM Cortex-M3 from sleep mode if enabled in

the NVIC.

7.7 Global Input Multiplexer Array (GIMA)

The GIMA routes signals to event-driven peripheral targets like the SCTimer/PWM,

timers, event router, or the ADCs.

7.7.1 Features

• Single selection of a source.

• Signal inversion.

• Can capture a pulse if the input event source is faster than the target clock.

• Synchronization of input event and target clock.

• Single-cycle pulse generation for target.

7.8 On-chip static RAM

The LPC185x/3x/2x/1x support up to 136 kB SRAM with separate bus master access for

higher throughput and individual power control for low-power operation.