Datasheet

LPC185X_3X_2X_1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.1 — 6 May 2014 63 of 148
NXP Semiconductors
LPC185x/3x/2x/1x
32-bit ARM Cortex-M3 microcontroller
7.9 On-chip flash memory
The LPC185x/3x/2x/1x contain up to 1 MB of dual-bank flash program memory. With
dual-bank flash memory, the user code can write or erase one flash bank while reading
the other flash bank without interruption. A two-port flash accelerator maximizes the flash
performance.
In-System Programming (ISP) and In-Application Programming (IAP) routines for
programming the flash memory are provided in the Boot ROM.
7.10 EEPROM
The LPC185x/3x/2x/1x contain up to 16 kB of on-chip byte-erasable and
byte-programmable EEPROM memory.
The EEPROM memory is divided into 128 pages. The user can access pages 1 through
127. Page 128 is protected.
7.11 Boot ROM
The internal ROM memory is used to store the boot code of the LPC185x/3x/2x/1x. After a
reset, the ARM processor will start its code execution from this memory.
The boot ROM memory includes the following features:
• The ROM memory size is 64 kB.
• Supports booting from external static memory such as NOR flash, SPI flash, quad SPI
flash, USB0, and USB1.
• Includes API for OTP programming.
• Includes a flexible USB device stack that supports Human Interface Device (HID),
Mass Storage Class (MSC), and Device Firmware Upgrade (DFU) drivers.
The default boot source is the flash memory. Several other boot modes are available if
P2_7 is LOW on reset depending on the values of the OTP bits BOOT_SRC. If the OTP
memory is not programmed or the BOOT_SRC bits are all zero, the states of the boot pins
P2_9, P2_8, P1_2, and P1_1 determine the boot mode.
Table 4. Boot mode when OTP BOOT_SRC bits are programmed
Boot mode BOOT_SRC
bit 3
BOOT_SRC
bit 2
BOOT_SRC
bit 1
BOOT_SRC
bit 0
Description
Pin state 0 0 0 0 The reset state of P1_1, P1_2, P2_8, and P2_9
pins determines the boot source. See Table 5
.
USART0 0 0 0 1 Enter ISP mode using USART0 functions on pins
P2_0 and P2_1.
SPIFI 0 0 1 0 Boot from Quad SPI flash connected to the SPIFI
interface using pins P3_3 to P3_8.
EMC 8-bit 0 0 1 1 Boot from external static memory (such as NOR
flash) using CS0 and an 8-bit data bus.
EMC 16-bit 0 1 0 0 Boot from external static memory (such as NOR
flash) using CS0 and a 16-bit data bus.
EMC 32-bit 0 1 0 1 Boot from external static memory (such as NOR
flash) using CS0 and a 32-bit data bus.