Datasheet

Product data sheet Rev. 4.1 — 6 May 2014 68 of 148

NXP Semiconductors

LPC185x/3x/2x/1x

32-bit ARM Cortex-M3 microcontroller

• Clock selection

• Inputs

• Events

• Outputs

• Interrupts

7.15.1.1 Features

• Two 16-bit counters or one 32-bit counter.

• Counters clocked by bus clock or selected input.

• Up counters or up-down counters.

• State variable allows sequencing across multiple counter cycles.

• The following conditions define an event: a counter match condition, an input (or

output) condition, a combination of a match and/or and input/output condition in a

specified state.

• Events control outputs, interrupts, and DMA requests.

– Match register 0 can be used as an automatic limit.

– In bi-directional mode, events can be enabled based on the count direction.

– Match events can be held until another qualifying event occurs.

• Selected events can limit, halt, start, or stop a counter.

• Supports:

– 8 inputs

– 16 outputs

– 16 match/capture registers

– 16 events

– 32 states

– Match register 0 to 5 support a fractional component for the dither engine

7.15.2 General-Purpose DMA

The DMA controller allows peripheral-to memory, memory-to-peripheral,

peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream

provides unidirectional serial DMA transfers for a single source and destination. For

example, a bidirectional port requires one stream for transmit and one for receives. The

source and destination areas can each be either a memory region or a peripheral for

master 1, but only memory for master 0.

7.15.2.1 Features

• Eight DMA channels. Each channel can support a unidirectional transfer.

• 16 DMA request lines.

• Single DMA and burst DMA request signals. Each peripheral connected to the DMA

Controller can assert either a burst DMA request or a single DMA request. The DMA

burst size is set by programming the DMA Controller.

• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral transfers are supported.