Datasheet

Product data sheet Rev. 4.1 — 6 May 2014 69 of 148

NXP Semiconductors

LPC185x/3x/2x/1x

32-bit ARM Cortex-M3 microcontroller

• Scatter or gather DMA is supported through the use of linked lists. This means that

the source and destination areas do not have to occupy contiguous areas of memory.

• Hardware DMA channel priority.

• AHB slave DMA programming interface. The DMA Controller is programmed by

writing to the DMA control registers over the AHB slave interface.

• Two AHB bus masters for transferring data. These interfaces transfer data when a

DMA request goes active. Master 1 can access memories and peripherals, master 0

can access memories only.

• 32-bit AHB master bus width.

• Incrementing or non-incrementing addressing for source and destination.

• Programmable DMA burst size. The DMA burst size can be programmed to more

efficiently transfer data.

• Internal four-word FIFO per channel.

• Supports 8, 16, and 32-bit wide transactions.

• Big-endian and little-endian support. The DMA Controller defaults to little-endian

mode on reset.

• An interrupt to the processor can be generated on a DMA completion or when a DMA

error has occurred.

• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read

prior to masking.

7.15.3 SPI Flash Interface (SPIFI)

The SPI Flash Interface allows low-cost serial flash memories to be connected to the ARM

Cortex-M3 processor with little performance penalty compared to parallel flash devices

with higher pin count.

After a few commands configure the interface at startup, the entire flash content is

accessible as normal memory using byte, halfword, and word accesses by the processor

and/or DMA channels. Simple sequences of commands handle erasure and

programming.

Many serial flash devices use a half-duplex command-driven SPI protocol for device setup

and initialization and then move to a half-duplex, command-driven 4-bit protocol for

normal operation. Different serial flash vendors and devices accept or require different

commands and command formats. SPIFI provides sufficient flexibility to be compatible

with common flash devices and includes extensions to help insure compatibility with future

devices.

7.15.3.1 Features

• Interfaces to serial flash memory in the main memory map.

• Supports classic and 4-bit bidirectional serial protocols.

• Half-duplex protocol compatible with various vendors and devices.

• Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to

52 MB per second.

• Supports DMA access.