Datasheet

LPC185X_3X_2X_1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.1 — 6 May 2014 83 of 148
NXP Semiconductors
LPC185x/3x/2x/1x
32-bit ARM Cortex-M3 microcontroller
The LPC185x/3x/2x/1x support four reduced power modes: Sleep, Deep-sleep,
Power-down, and Deep power-down.
The LPC185x/3x/2x/1x can wake up from Deep-sleep, Power-down, and Deep
power-down modes via the WAKEUP[3:0] pins and interrupts generated by battery
powered blocks in the RTC power domain.
7.20.10 Code security (Code Read Protection - CRP)
CRP enables different levels of security so that access to the on-chip flash and use of the
JTAG and ISP can be restricted. CRP is invoked by programming a specific pattern into a
dedicated flash location. IAP commands are not affected by CRP.
Fig 9. LPC185x/3x/2x/1x Power domains
REAL-TIME CLOCK
BACKUP REGISTERS
RESET/WAKE-UP
CONTROL
REGULATOR
32 kHz
OSCILLATOR
ALWAYS-ON/RTC POWER DOMAIN
MAIN POWER DOMAIN
RTCX1
VBAT
VDDREG
RTCX2
VDDIO
VSS
to memories,
peripherals,
oscillators,
PLLs
to core
to I/O pads
ADC
DAC
OTP
ADC POWER DOMAIN
OTP POWER DOMAIN
USB0 POWER DOMAIN
VDDA
VSSA
VPP
USB0
USB0_VDDA3V3_DRIVER
USB0_VDDA3V3
LPC18xx
ULTRA LOW-POWER
REGULATOR
ALARM
RESET
WAKEUP0/1/2/3
to RTC
domain
peripherals
002aag305
to RTC I/O
pads (V
ps
)