Datasheet

Product data sheet Rev. 4.1 — 6 May 2014 84 of 148

NXP Semiconductors

LPC185x/3x/2x/1x

32-bit ARM Cortex-M3 microcontroller

There are three levels of the Code Read Protection:

• In level CRP1, access to the chip via the JTAG is disabled. Partial flash updates are

allowed (excluding flash sector 0) using a limited set of the ISP commands. This level

is useful when CRP is required and flash field updates are needed. CRP1 does

prevent the user code from erasing all sectors.

• In level CRP2, access to the chip via the JTAG is disabled. Only a full flash erase and

update using a reduced set of the ISP commands is allowed.

• In level CRP3, any access to the chip via the JTAG pins or the ISP is disabled. This

mode also disables the ISP override using P2_7 pin. If necessary, the application

code must provide a flash update mechanism using the IAP calls or using the

reinvoke ISP command to enable flash update via USART0. See Table 5

7.21 Emulation and debugging

Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and

trace functions are supported in addition to a standard JTAG debug and parallel trace

functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four

watch points.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.