Datasheet

LPC185X_3X_2X_1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.1 — 6 May 2014 95 of 148
NXP Semiconductors
LPC185x/3x/2x/1x
32-bit ARM Cortex-M3 microcontroller
Conditions: active mode entered executing code while (1){} from SRAM; V
DD(REG)(3V3)
= 3.3 V;
system PLL enabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled.
Fig 12. Typical supply current versus core frequency in active mode; code executed from
SRAM
Conditions: V
DD(REG)(3V3)
= 3.3 V; internal pull-up resistors disabled; system PLL disabled; IRC
enabled; all peripherals disabled; all peripheral clocks disabled. CCLK = 12 MHz.
Fig 13. Typical supply current versus temperature in sleep mode
aaa-013046
12 36 60 84 108 132 156 180
0
20
40
60
80
100
frequency (MHz)
I
DD(REG)(3V3)DD(REG)(3V3)
I
DD(REG)(3V3)
(mA)(mA)(mA)
+105 °C
+90 °C
+25 °C
0 °C
-40 °C
aaa-013047
-40 -20 0 20 40 60 80 100 120
0
5
10
15
20
temperature (°C)
I
DD(REG)(3V3)
DD(REG)(3V3)
I
DD(REG)(3V3)
(mA)
(mA)
(mA)