Datasheet

LPC2104_2105_2106_7 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 07 — 20 June 2008 4 of 41
NXP Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
4. Block diagram
(1) Shared with GPIO.
(2) When test/debug interface is used, GPIO/other functions sharing these pins are not available.
(3) Available on LPC2104/2105/2106/01 only.
Fig 1. Block diagram
SCL
(1)
P0[31:0]
TRST
(2)
TMS
(2)
TCK
(2)
TDI
(2)
TDO
(2)
XTAL2
XTAL1
EINT[2:0]
(1)
AHB BRIDGE
PLL
PWM0
ARM7TDMI-S
LPC2104/2105/2106
RESET
CAP0[2:0]
(1)
CAP1[3:0]
(1)
MAT0[2:0]
(1)
MAT1[3:0]
(1)
SDA
(1)
RXD[1:0]
(1)
TXD[1:0]
(1)
DSR1
(1)
, CTS1
(1)
,
RTS1
(1)
, DTR1
(1)
,
DCD1
(1)
, RI1
(1)
RTCK
ARM7 LOCAL BUS
INTERNAL
SRAM
CONTROLLER
INTERNAL
FLASH
CONTROLLER
16/32/64 kB
SRAM
128 kB
FLASH
EXTERNAL
INTERRUPTS
CAPTURE/
COMPARE
TIMER 0/TIMER 1
GENERAL
PURPOSE I/O
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
AMBA Advanced High-performance
Bus (AHB)
system
clock
SYSTEM
FUNCTIONS
VECTORED
INTERRUPT
CONTROLLER
AHB
DECODER
I
2
C-BUS SERIAL
INTERFACE
AHB TO APB
BRIDGE
APB
DIVIDER
Advanced Peripheral
Bus (APB)
UART0/UART1
WATCHDOG
TIMER
SYSTEM
CONTROL
REAL-TIME CLOCK
002aaa412
V
DD(3V3)
V
SS
V
DD(1V8)
PWM[6:1]
(1)
P0
HIGH-SPEED
GPIO
(3)
32 PINS TOTAL
SCK
(1)
MOSI
(1)
MISO
(1)
SSEL
(1)
SPI/SSP
(3)
SERIAL INTERFACE