Datasheet

LPC2194_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 11 September 2006 7 of 36
Philips Semiconductors
LPC2194
Single-chip 16/32-bit microcontroller
P0.30/AIN3/
EINT3/CAP0.0
15 I AIN3 — A/D converter, input 3. This analog input is always connected to its pin.
I EINT3 — External interrupt 3 input.
I CAP0.0 — Capture input for Timer 0, channel 0.
P1.0 to P1.31 I/O Port 1 is a 32-bit bidirectional I/O port with individual direction controls for each bit.
The operation of port 1 pins depends upon the pin function selected via the Pin
Connect Block. Pins 0 through 15 of port 1 are not available.
P1.16/
TRACEPKT0
16 O Trace Packet, bit 0. Standard I/O port with internal pull-up.
P1.17/
TRACEPKT1
12 O Trace Packet, bit 1. Standard I/O port with internal pull-up.
P1.18/
TRACEPKT2
8 O Trace Packet, bit 2. Standard I/O port with internal pull-up.
P1.19/
TRACEPKT3
4 O Trace Packet, bit 3. Standard I/O port with internal pull-up.
P1.20/
TRACESYNC
48 O Trace Synchronization. Standard I/O port with internal pull-up.
Note: LOW on this pin while RESET
is LOW, enables pins P1[25:16] to operate as
Trace port after reset.
P1.21/PIPESTAT0 44 O Pipeline Status, bit 0. Standard I/O port with internal pull-up.
P1.22/PIPESTAT1 40 O Pipeline Status, bit 1. Standard I/O port with internal pull-up.
P1.23/PIPESTAT2 36 O Pipeline Status, bit 2. Standard I/O port with internal pull-up.
P1.24/TRACECLK 32 O Trace Clock. Standard I/O port with internal pull-up.
P1.25/EXTIN0 28 I External Trigger Input. Standard I/O with internal pull-up.
P1.26/RTCK 24 I/O Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger
synchronization when processor frequency varies. Bidirectional pin with internal
pull-up.
Note: LOW on this pin while RESET
is LOW, enables pins P1[31:26] to operate as
Debug port after reset.
P1.27/TDO 64 O Test Data out for JTAG interface.
P1.28/TDI 60 I Test Data in for JTAG interface.
P1.29/TCK 56 I Test Clock for JTAG interface.
P1.30/TMS 52 I Test Mode Select for JTAG interface.
P1.31/TRST
20 I Test Reset for JTAG interface.
TD1 10 O CAN1 transmitter output.
RESET
57 I external reset input; a LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor execution to begin at
address 0. TTL with hysteresis, 5 V tolerant.
XTAL1 62 I input to the oscillator circuit and internal clock generator circuits
XTAL2 61 O output from the oscillator amplifier
V
SS
6, 18, 25,
42, 50
I ground: 0 V reference
V
SSA
59 I analog ground; 0 V reference. This should nominally be the same voltage as V
SS
,
but should be isolated to minimize noise and error.
V
SSA(PLL)
58 I PLL analog ground; 0 V reference. This should nominally be the same voltage as
V
SS
, but should be isolated to minimize noise and error.
V
DD(1V8)
17, 49 I 1.8 V core power supply; this is the power supply voltage for internal circuitry.
Table 2. Pin description …continued
Symbol Pin Type Description