Datasheet

Product data sheet Rev. 8 — 8 June 2011 21 of 54

NXP Semiconductors

LPC2292/2294

16/32-bit ARM microcontrollers with external memory interface

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I

C-bus is a multi-master bus, it can be

controlled by more than one bus master connected to it.

The I

C-bus implemented in LPC2292/2294 supports bit rate up to 400 kbit/s (Fast

C-bus).

6.12.1 Features

• Compliant with standard I

C-bus interface.

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I

C-bus may be used for test and diagnostic purposes.

6.13 SPI serial I/O controller

The LPC2292/2294 each contain two SPIs. The SPI is a full duplex serial interface,

designed to be able to handle multiple masters and slaves connected to a given bus. Only

a single master and a single slave can communicate on the interface during a given data

transfer. During a data transfer the master always sends a byte of data to the slave, and

the slave always sends a byte of data to the master.

6.13.1 Features

• Compliant with Serial Peripheral Interface (SPI) specification.

• Synchronous, Serial, Full Duplex communication.

• Combined SPI master and slave.

• Maximum data bit rate of

⁄

of the input clock rate.

6.13.2 Features available in LPC2292/2294/01 only

• Eight to 16 bits per frame.

• When the SPI interface is used in Master mode, the SSELn pin is not needed (can be

used for a different function).