Datasheet
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Applications
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 7.1 Architectural overview
- 7.2 On-chip flash programming memory
- 7.3 On-chip SRAM
- 7.4 Memory map
- 7.5 Interrupt controller
- 7.6 Pin connect block
- 7.7 General purpose DMA controller
- 7.8 Fast general purpose parallel I/O
- 7.9 Ethernet (LPC2362 only)
- 7.10 USB interface
- 7.11 CAN controller and acceptance filters
- 7.12 10-bit ADC
- 7.13 10-bit DAC
- 7.14 UARTs
- 7.15 SPI serial I/O controller
- 7.16 SSP serial I/O controller
- 7.17 I2C-bus serial I/O controllers
- 7.18 I2S-bus serial I/O controllers
- 7.19 General purpose 32-bit timers/external event counters
- 7.20 Pulse width modulator
- 7.21 Watchdog timer
- 7.22 RTC and battery RAM
- 7.23 Clocking and power control
- 7.24 System control
- 7.25 Emulation and debugging
- 8. Limiting values
- 9. Thermal characteristics
- 10. Static characteristics
- 11. Dynamic characteristics
- 12. ADC electrical characteristics
- 13. DAC electrical characteristics
- 14. Application information
- 15. Package outline
- 16. Abbreviations
- 17. Revision history
- 18. Legal information
- 19. Contact information
- 20. Contents
LPC2361_62 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5.1 — 15 October 2013 10 of 65
NXP Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit MCU
P1[30]/V
BUS
/AD0[4] 21
[2]
I/O P1[30] — General purpose digital input/output pin.
I V
BUS
— Monitors the presence of USB bus power.
Note: This signal must be HIGH for USB reset to occur.
I AD0[4] — A/D converter 0, input 4.
P1[31]/SCK1/AD0[5] 20
[2]
I/O P1[31] — General purpose digital input/output pin.
I/O SCK1 — Serial Clock for SSP1.
I AD0[5] — A/D converter 0, input 5.
P2[0] to P2[31] I/O Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The
operation of port 2 pins depends upon the pin function selected via the pin
connect block. Pins 14 through 31 of this port are not available.
P2[0]/PWM1[1]/
TXD1/TRACECLK
75
[1]
I/O P2[0] — General purpose digital input/output pin.
O PWM1[1] — Pulse Width Modulator 1, channel 1 output.
O TXD1 — Transmitter output for UART1.
O TRACECLK — Trace Clock.
P2[1]/PWM1[2]/
RXD1/PIPESTAT0
74
[1]
I/O P2[1] — General purpose digital input/output pin.
O PWM1[2] — Pulse Width Modulator 1, channel 2 output.
I RXD1 — Receiver input for UART1.
O PIPESTAT0 — Pipeline Status, bit 0.
P2[2]/PWM1[3]/
CTS1/PIPESTAT1
73
[1]
I/O P2[2] — General purpose digital input/output pin.
O PWM1[3] — Pulse Width Modulator 1, channel 3 output.
I CTS1 — Clear to Send input for UART1.
O PIPESTAT1 — Pipeline Status, bit 1.
P2[3]/PWM1[4]/
DCD1/PIPESTAT2
70
[1]
I/O P2[3] — General purpose digital input/output pin.
O PWM1[4] — Pulse Width Modulator 1, channel 4 output.
I DCD1 — Data Carrier Detect input for UART1.
O PIPESTAT2 — Pipeline Status, bit 2.
P2[4]/PWM1[5]/
DSR1/TRACESYNC
69
[1]
I/O P2[4] — General purpose digital input/output pin.
O PWM1[5] — Pulse Width Modulator 1, channel 5 output.
I DSR1 — Data Set Ready input for UART1.
O TRACESYNC — Trace Synchronization.
P2[5]/PWM1[6]/
DTR1/TRACEPKT0
68
[1]
I/O P2[5] — General purpose digital input/output pin.
O PWM1[6] — Pulse Width Modulator 1, channel 6 output.
O DTR1 — Data Terminal Ready output for UART1.
O TRACEPKT0 — Trace Packet, bit 0.
P2[6]/PCAP1[0]/RI1/
TRACEPKT1
67
[1]
I/O P2[6] — General purpose digital input/output pin.
I PCAP1[0] — Capture input for PWM1, channel 0.
I RI1 — Ring Indicator input for UART1.
O TRACEPKT1 — Trace Packet, bit 1.
Table 3. Pin description
…continued
Symbol Pin Type Description
