Datasheet
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Applications
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 7.1 Architectural overview
- 7.2 On-chip flash programming memory
- 7.3 On-chip SRAM
- 7.4 Memory map
- 7.5 Interrupt controller
- 7.6 Pin connect block
- 7.7 General purpose DMA controller
- 7.8 Fast general purpose parallel I/O
- 7.9 Ethernet (LPC2362 only)
- 7.10 USB interface
- 7.11 CAN controller and acceptance filters
- 7.12 10-bit ADC
- 7.13 10-bit DAC
- 7.14 UARTs
- 7.15 SPI serial I/O controller
- 7.16 SSP serial I/O controller
- 7.17 I2C-bus serial I/O controllers
- 7.18 I2S-bus serial I/O controllers
- 7.19 General purpose 32-bit timers/external event counters
- 7.20 Pulse width modulator
- 7.21 Watchdog timer
- 7.22 RTC and battery RAM
- 7.23 Clocking and power control
- 7.24 System control
- 7.25 Emulation and debugging
- 8. Limiting values
- 9. Thermal characteristics
- 10. Static characteristics
- 11. Dynamic characteristics
- 12. ADC electrical characteristics
- 13. DAC electrical characteristics
- 14. Application information
- 15. Package outline
- 16. Abbreviations
- 17. Revision history
- 18. Legal information
- 19. Contact information
- 20. Contents
LPC2361_62 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5.1 — 15 October 2013 20 of 65
NXP Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit MCU
• Scalable realization of endpoints at run time.
• Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
• Supports SoftConnect and GoodLink features.
• While the USB is in the Suspend mode, the LPC2361/2362 can enter one of the
reduced power modes and wake up on USB activity.
• Supports DMA transfers with the DMA RAM of 16 kB on all non-control endpoints.
• Allows dynamic switching between CPU-controlled and DMA modes.
• Double buffer implementation for Bulk and Isochronous endpoints.
7.10.2 USB host controller
The host controller enables full- and low-speed data exchange with USB devices attached
to the bus. It consists of register interface, serial interface engine, and DMA controller. The
register interface complies with the OHCI specification.
7.10.2.1 Features
• OHCI compliant.
• Two downstream ports.
• Supports per-port power switching.
7.10.3 USB OTG controller
USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that augments the
capability of existing mobile devices and USB peripherals by adding host functionality for
connection to USB peripherals.
The OTG Controller integrates the Host Controller, device controller, and a master-only
I
2
C interface to implement OTG dual-role device functionality. The dedicated I
2
C interface
controls an external OTG transceiver.
7.10.3.1 Features
• Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision
1.0a.
• Hardware support for Host Negotiation Protocol (HNP).
• Includes a programmable timer required for HNP and Session Request Protocol
(SRP).
• Supports any OTG transceiver compliant with the OTG Transceiver Specification
(CEA-2011), Rev. 1.0.
7.11 CAN controller and acceptance filters
The Controller Area Network (CAN) is a serial communications protocol which efficiently
supports distributed real-time control with a very high level of security. Its domain of
application ranges from high-speed networks to low cost multiplex wiring.
The CAN block is intended to support multiple CAN buses simultaneously, allowing the
device to be used as a gateway, switch, or router among a number of CAN buses in
industrial or automotive applications.