Datasheet
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Applications
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 7.1 Architectural overview
- 7.2 On-chip flash programming memory
- 7.3 On-chip SRAM
- 7.4 Memory map
- 7.5 Interrupt controller
- 7.6 Pin connect block
- 7.7 General purpose DMA controller
- 7.8 Fast general purpose parallel I/O
- 7.9 Ethernet (LPC2362 only)
- 7.10 USB interface
- 7.11 CAN controller and acceptance filters
- 7.12 10-bit ADC
- 7.13 10-bit DAC
- 7.14 UARTs
- 7.15 SPI serial I/O controller
- 7.16 SSP serial I/O controller
- 7.17 I2C-bus serial I/O controllers
- 7.18 I2S-bus serial I/O controllers
- 7.19 General purpose 32-bit timers/external event counters
- 7.20 Pulse width modulator
- 7.21 Watchdog timer
- 7.22 RTC and battery RAM
- 7.23 Clocking and power control
- 7.24 System control
- 7.25 Emulation and debugging
- 8. Limiting values
- 9. Thermal characteristics
- 10. Static characteristics
- 11. Dynamic characteristics
- 12. ADC electrical characteristics
- 13. DAC electrical characteristics
- 14. Application information
- 15. Package outline
- 16. Abbreviations
- 17. Revision history
- 18. Legal information
- 19. Contact information
- 20. Contents
LPC2361_62 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5.1 — 15 October 2013 26 of 65
NXP Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit MCU
• Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become
effective.
• May be used as a standard timer if the PWM mode is not enabled.
• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
7.21 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
7.21.1 Features
• Internally resets chip if not periodically reloaded.
• Debug mode.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 32-bit timer with internal prescaler.
• Selectable time period from (T
cy(WDCLK)
256 4) to (T
cy(WDCLK)
2
32
4) in
multiples of T
cy(WDCLK)
4.
• The Watchdog Clock (WDCLK) source can be selected from the RTC clock, the
Internal RC oscillator (IRC), or the APB peripheral clock. This gives a wide range of
potential timing choices of watchdog operation under different power reduction
conditions. It also provides the ability to run the WDT from an entirely internal source
that is not dependent on an external crystal and its associated components and
wiring, for increased reliability.
7.22 RTC and battery RAM
The RTC is a set of counters for measuring time when system power is on, and optionally
when it is off. It uses little power in Power-down and Deep power-down modes. On the
LPC2361/2362, the RTC can be clocked by a separate 32.768 kHz oscillator, or by a
programmable prescale divider based on the APB clock. Also, the RTC is powered by its
own power supply pin, VBAT, which can be connected to a battery or to the same 3.3 V
supply used by the rest of the device.
The VBAT pin supplies power only to the RTC and the battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
7.22.1 Features
• Measures the passage of time to maintain a calendar and clock.
• Ultra low power design to support battery powered systems.
• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and
Day of Year.
