Datasheet
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Applications
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 7.1 Architectural overview
- 7.2 On-chip flash programming memory
- 7.3 On-chip SRAM
- 7.4 Memory map
- 7.5 Interrupt controller
- 7.6 Pin connect block
- 7.7 General purpose DMA controller
- 7.8 Fast general purpose parallel I/O
- 7.9 Ethernet (LPC2362 only)
- 7.10 USB interface
- 7.11 CAN controller and acceptance filters
- 7.12 10-bit ADC
- 7.13 10-bit DAC
- 7.14 UARTs
- 7.15 SPI serial I/O controller
- 7.16 SSP serial I/O controller
- 7.17 I2C-bus serial I/O controllers
- 7.18 I2S-bus serial I/O controllers
- 7.19 General purpose 32-bit timers/external event counters
- 7.20 Pulse width modulator
- 7.21 Watchdog timer
- 7.22 RTC and battery RAM
- 7.23 Clocking and power control
- 7.24 System control
- 7.25 Emulation and debugging
- 8. Limiting values
- 9. Thermal characteristics
- 10. Static characteristics
- 11. Dynamic characteristics
- 12. ADC electrical characteristics
- 13. DAC electrical characteristics
- 14. Application information
- 15. Package outline
- 16. Abbreviations
- 17. Revision history
- 18. Legal information
- 19. Contact information
- 20. Contents
LPC2361_62 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5.1 — 15 October 2013 38 of 65
NXP Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit MCU
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2] The RTC typically fails when V
i(VBAT)
drops below 1.6 V.
[3] V
DD(DCDC)(3V3)
= 3.3 V; V
DD(3V3)
= 3.3 V; V
i(VBAT)
= 3.3 V; T
amb
=25C.
[4] On pin VBAT.
[5] Including voltage on outputs in 3-state mode.
[6] V
DD(3V3)
supply voltages must be present.
[7] 3-state outputs go into 3-state mode when V
DD(3V3)
is grounded.
[8] Please also see the errata note mentioned in errata sheet.
[9] Accounts for 100 mV voltage drop in all supply lines.
[10] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[11] Minimum condition for V
I
= 4.5 V, maximum condition for V
I
=5.5V.
[12] To V
SS
.
[13] Includes external resistors of 33 1 % on D+ and D.
USB pins
I
OZ
OFF-state output
current
0V<V
I
<3.3V - - 10 A
V
BUS
bus supply voltage - - 5.25 V
V
DI
differential input
sensitivity voltage
(D+) (D) 0.2 - - V
V
CM
differential common
mode voltage range
includes V
DI
range 0.8 - 2.5 V
V
th(rs)se
single-ended receiver
switching threshold
voltage
0.8 - 2.0 V
V
OL
LOW-level output
voltage for
low-/full-speed
R
L
of 1.5 k to 3.6 V - - 0.18 V
V
OH
HIGH-level output
voltage (driven) for
low-/full-speed
R
L
of 15 k to GND 2.8 - 3.5 V
C
trans
transceiver capacitance pin to GND - - 20 pF
Z
DRV
driver output
impedance for driver
which is not high-speed
capable
with 33 series resistor;
steady state drive
[13]
36 - 44.1
Table 7. Static characteristics …continued
T
amb
=
40
C to +85
C for commercial applications, unless otherwise specified.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
