Datasheet
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Applications
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 7.1 Architectural overview
- 7.2 On-chip flash programming memory
- 7.3 On-chip SRAM
- 7.4 Memory map
- 7.5 Interrupt controller
- 7.6 Pin connect block
- 7.7 General purpose DMA controller
- 7.8 Fast general purpose parallel I/O
- 7.9 Ethernet (LPC2362 only)
- 7.10 USB interface
- 7.11 CAN controller and acceptance filters
- 7.12 10-bit ADC
- 7.13 10-bit DAC
- 7.14 UARTs
- 7.15 SPI serial I/O controller
- 7.16 SSP serial I/O controller
- 7.17 I2C-bus serial I/O controllers
- 7.18 I2S-bus serial I/O controllers
- 7.19 General purpose 32-bit timers/external event counters
- 7.20 Pulse width modulator
- 7.21 Watchdog timer
- 7.22 RTC and battery RAM
- 7.23 Clocking and power control
- 7.24 System control
- 7.25 Emulation and debugging
- 8. Limiting values
- 9. Thermal characteristics
- 10. Static characteristics
- 11. Dynamic characteristics
- 12. ADC electrical characteristics
- 13. DAC electrical characteristics
- 14. Application information
- 15. Package outline
- 16. Abbreviations
- 17. Revision history
- 18. Legal information
- 19. Contact information
- 20. Contents
LPC2361_62 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5.1 — 15 October 2013 45 of 65
NXP Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit MCU
11.4 Flash memory
[1] Number of program/erase cycles.
[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes.
11.5 Timing
Table 12. Dynamic characteristics of flash
T
amb
=
40
C to +85
C, unless otherwise specified; V
DD(3V3)
= 3.0 V to 3.6 V; all voltages are measured with respect to
ground.
Symbol Parameter Conditions Min Typ Max Unit
N
endu
endurance
[1]
10000 100000 - cycles
t
ret
retention time powered; 100 cycles
[2]
10--years
unpowered; 100 cycles 20 - - years
t
er
erase time sector or multiple
consecutive sectors
95 100 105 ms
t
prog
programming time
[2]
0.95 1 1.05 ms
Fig 13. Differential data-to-EOP transition skew and EOP width
002aab561
T
PERIOD
differential
data lines
crossover point
source EOP width: t
FEOPT
receiver EOP width: t
EOPR1
, t
EOPR2
crossover point
extended
differential data to
SE0/EOP skew
n × T
PERIOD
+ t
FDEOP
