Datasheet
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Applications
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 7.1 Architectural overview
- 7.2 On-chip flash programming memory
- 7.3 On-chip SRAM
- 7.4 Memory map
- 7.5 Interrupt controller
- 7.6 Pin connect block
- 7.7 General purpose DMA controller
- 7.8 Fast general purpose parallel I/O
- 7.9 Ethernet (LPC2362 only)
- 7.10 USB interface
- 7.11 CAN controller and acceptance filters
- 7.12 10-bit ADC
- 7.13 10-bit DAC
- 7.14 UARTs
- 7.15 SPI serial I/O controller
- 7.16 SSP serial I/O controller
- 7.17 I2C-bus serial I/O controllers
- 7.18 I2S-bus serial I/O controllers
- 7.19 General purpose 32-bit timers/external event counters
- 7.20 Pulse width modulator
- 7.21 Watchdog timer
- 7.22 RTC and battery RAM
- 7.23 Clocking and power control
- 7.24 System control
- 7.25 Emulation and debugging
- 8. Limiting values
- 9. Thermal characteristics
- 10. Static characteristics
- 11. Dynamic characteristics
- 12. ADC electrical characteristics
- 13. DAC electrical characteristics
- 14. Application information
- 15. Package outline
- 16. Abbreviations
- 17. Revision history
- 18. Legal information
- 19. Contact information
- 20. Contents
LPC2361_62 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5.1 — 15 October 2013 47 of 65
NXP Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit MCU
12. ADC electrical characteristics
[1] Conditions: V
SSA
=0V, V
DDA
=3.3V.
[2] The ADC is monotonic, there are no missing codes.
[3] The differential linearity error (E
D
) is the difference between the actual step width and the ideal step width. See Figure 15.
[4] The integral non-linearity (E
L(adj)
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 15
.
[5] The offset error (E
O
) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 15
.
[6] The gain error (E
G
) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 15
.
[7] The absolute error (E
T
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 15
.
[8] See Figure 16
.
Table 13. ADC characteristics
V
DDA
= 2.5 V to 3.6 V; T
amb
=
40
C to +85
C, unless otherwise specified; ADC frequency 4.5 MHz.
Symbol Parameter Conditions Min Typ Max Unit
V
IA
analog input voltage 0 - V
DDA
V
C
ia
analog input capacitance - - 1 pF
E
D
differential linearity error
[1][2][3]
--1LSB
E
L(adj)
integral non-linearity
[1][4]
--2LSB
E
O
offset error
[1][5]
--3LSB
E
G
gain error
[1][6]
--0.5 %
E
T
absolute error
[1][7]
--4LSB
R
vsi
voltage source interface
resistance
[8]
--40k
