Datasheet
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Applications
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 7.1 Architectural overview
- 7.2 On-chip flash programming memory
- 7.3 On-chip SRAM
- 7.4 Memory map
- 7.5 Interrupt controller
- 7.6 Pin connect block
- 7.7 General purpose DMA controller
- 7.8 Fast general purpose parallel I/O
- 7.9 Ethernet (LPC2362 only)
- 7.10 USB interface
- 7.11 CAN controller and acceptance filters
- 7.12 10-bit ADC
- 7.13 10-bit DAC
- 7.14 UARTs
- 7.15 SPI serial I/O controller
- 7.16 SSP serial I/O controller
- 7.17 I2C-bus serial I/O controllers
- 7.18 I2S-bus serial I/O controllers
- 7.19 General purpose 32-bit timers/external event counters
- 7.20 Pulse width modulator
- 7.21 Watchdog timer
- 7.22 RTC and battery RAM
- 7.23 Clocking and power control
- 7.24 System control
- 7.25 Emulation and debugging
- 8. Limiting values
- 9. Thermal characteristics
- 10. Static characteristics
- 11. Dynamic characteristics
- 12. ADC electrical characteristics
- 13. DAC electrical characteristics
- 14. Application information
- 15. Package outline
- 16. Abbreviations
- 17. Revision history
- 18. Legal information
- 19. Contact information
- 20. Contents
LPC2361_62 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5.1 — 15 October 2013 5 of 65
NXP Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit MCU
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. LPC2361/2362 pinning
LPC2361FBD100
LPC2362FBD100
75
26
50
100
76
51
1
25
002aad965
Table 3. Pin description
Symbol Pin Type Description
P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The
operation of port 0 pins depends upon the pin function selected via the pin
connect block. Pins 12, 13, 14, and 31 of this port are not available.
P0[0]/RD1/TXD3/
SDA1
46
[1]
I/O P0[0] — General purpose digital input/output pin.
I RD1 — CAN1 receiver input.
O TXD3 — Transmitter output for UART3.
I/O SDA1 — I
2
C1 data input/output (this is not an open-drain pin).
P0[1]/TD1/RXD3/
SCL1
47
[1]
I/O P0[1] — General purpose digital input/output pin.
O TD1 — CAN1 transmitter output.
I RXD3 — Receiver input for UART3.
I/O SCL1 — I
2
C1 clock input/output (this is not an open-drain pin).
P0[2]/TXD0 98
[1]
I/O P0[2] — General purpose digital input/output pin.
O TXD0 — Transmitter output for UART0.
P0[3]/RXD0 99
[1]
I/O P0[3] — General purpose digital input/output pin.
I RXD0 — Receiver input for UART0.
P0[4]/I2SRX_CLK/
RD2/CAP2[0]
81
[1]
I/O P0[4] — General purpose digital input/output pin.
I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the
slave. Corresponds to the signal SCK in the I
2
S-bus specification.
I RD2 — CAN2 receiver input.
I CAP2[0] — Capture input for Timer 2, channel 0.
