Datasheet
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Applications
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 7.1 Architectural overview
- 7.2 On-chip flash programming memory
- 7.3 On-chip SRAM
- 7.4 Memory map
- 7.5 Interrupt controller
- 7.6 Pin connect block
- 7.7 General purpose DMA controller
- 7.8 Fast general purpose parallel I/O
- 7.9 Ethernet (LPC2362 only)
- 7.10 USB interface
- 7.11 CAN controller and acceptance filters
- 7.12 10-bit ADC
- 7.13 10-bit DAC
- 7.14 UARTs
- 7.15 SPI serial I/O controller
- 7.16 SSP serial I/O controller
- 7.17 I2C-bus serial I/O controllers
- 7.18 I2S-bus serial I/O controllers
- 7.19 General purpose 32-bit timers/external event counters
- 7.20 Pulse width modulator
- 7.21 Watchdog timer
- 7.22 RTC and battery RAM
- 7.23 Clocking and power control
- 7.24 System control
- 7.25 Emulation and debugging
- 8. Limiting values
- 9. Thermal characteristics
- 10. Static characteristics
- 11. Dynamic characteristics
- 12. ADC electrical characteristics
- 13. DAC electrical characteristics
- 14. Application information
- 15. Package outline
- 16. Abbreviations
- 17. Revision history
- 18. Legal information
- 19. Contact information
- 20. Contents
LPC2361_62 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5.1 — 15 October 2013 6 of 65
NXP Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit MCU
P0[5]/I2SRX_WS/
TD2/CAP2[1]
80
[1]
I/O P0[5] — General purpose digital input/output pin.
I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the
slave. Corresponds to the signal WS in the I
2
S-bus specification.
O TD2 — CAN2 transmitter output.
I CAP2[1] — Capture input for Timer 2, channel 1.
P0[6]/I2SRX_SDA/
SSEL1/MAT2[0]
79
[1]
I/O P0[6] — General purpose digital input/output pin.
I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I
2
S-bus specification.
I/O SSEL1 — Slave Select for SSP1.
O MAT2[0] — Match output for Timer 2, channel 0.
P0[7]/I2STX_CLK/
SCK1/MAT2[1]
78
[1]
I/O P0[7] — General purpose digital input/output pin.
I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the
slave. Corresponds to the signal SCK in the I
2
S-bus specification.
I/O SCK1 — Serial Clock for SSP1.
O MAT2[1] — Match output for Timer 2, channel 1.
P0[8]/I2STX_WS/
MISO1/MAT2[2]
77
[1]
I/O P0[8] — General purpose digital input/output pin.
I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by
the slave. Corresponds to the signal WS in the I
2
S-bus specification.
I/O MISO1 — Master In Slave Out for SSP1.
O MAT2[2] — Match output for Timer 2, channel 2.
P0[9]/I2STX_SDA/
MOSI1/MAT2[3]
76
[1]
I/O P0[9] — General purpose digital input/output pin.
I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I
2
S-bus specification.
I/O MOSI1 — Master Out Slave In for SSP1.
O MAT2[3] — Match output for Timer 2, channel 3.
P0[10]/TXD2/
SDA2/MAT3[0]
48
[1]
I/O P0[10] — General purpose digital input/output pin.
O TXD2 — Transmitter output for UART2.
I/O SDA2 — I
2
C2 data input/output (this is not an open-drain pin).
O MAT3[0] — Match output for Timer 3, channel 0.
P0[11]/RXD2/
SCL2/MAT3[1]
49
[1]
I/O P0[11] — General purpose digital input/output pin.
I RXD2 — Receiver input for UART2.
I/O SCL2 — I
2
C2 clock input/output (this is not an open-drain pin).
O MAT3[1] — Match output for Timer 3, channel 1.
P0[15]/TXD1/
SCK0/SCK
62
[1]
I/O P0[15] — General purpose digital input/output pin.
O TXD1 — Transmitter output for UART1.
I/O SCK0 — Serial clock for SSP0.
I/O SCK — Serial clock for SPI.
P0[16]/RXD1/
SSEL0/SSEL
63
[1]
I/O P0[16] — General purpose digital input/output pin.
I RXD1 — Receiver input for UART1.
I/O SSEL0 — Slave Select for SSP0.
I/O SSEL — Slave Select for SPI.
Table 3. Pin description
…continued
Symbol Pin Type Description
