Datasheet

LPC2377_78 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6.1 — 16 October 2013 14 of 69
NXP Semiconductors
LPC2377/78
Single-chip 16-bit/32-bit microcontrollers
P4[24]/OE 127
[1]
I/O P4[24] — General purpose digital input/output pin.
O OE
— LOW active Output Enable signal.
P4[25]/BLS0
124
[1]
I/O P4[25] — General purpose digital input/output pin.
O BLS0
— LOW active Byte Lane select signal 0.
P4[28]/MAT2[0]/
TXD3
118
[1]
I/O P4[28] — General purpose digital input/output pin.
O MAT2[0] — Match output for Timer 2, channel 0.
O TXD3 — Transmitter output for UART3.
P4[29]/MAT2[1]/
RXD3
122
[1]
I/O P4[29] — General purpose digital input/output pin.
O MAT2[1] — Match output for Timer 2, channel 1.
I RXD3 — Receiver input for UART3.
P4[30]/CS0
130
[1]
I/O P4[30] — General purpose digital input/output pin.
O CS0
— LOW active Chip Select 0 signal.
P4[31]/CS1
134
[1]
I/O P4[31] — General purpose digital input/output pin.
O CS1
— LOW active Chip Select 1 signal.
ALARM 26
[8]
O ALARM — RTC controlled output. This pin is 1.8 V. It goes HIGH when an RTC
alarm is generated.
USB_D2 37 I/O USB_D2 — USB2 port bidirectional D line. LPC2378 only. This pin is not
connected on the LPC2377.
DBGEN 6
[1][9]
I DBGEN — JTAG interface control signal. Also used for boundary scanning.
TDO 1
[1][10]
O TDO — Test Data out for JTAG interface.
TDI 3
[1][9]
I TDI — Test Data in for JTAG interface.
TMS 4
[1][9]
I TMS — Test Mode Select for JTAG interface.
TRST
5
[1][9]
I TRST — Test Reset for JTAG interface.
TCK 7
[1][10]
I TCK — Test Clock for JTAG interface. This clock must be slower than
1
⁄
6
of the CPU
clock (CCLK) for the JTAG interface to operate.
RTCK 143
[1][9]
I/O RTCK — JTAG interface control signal.
Note: LOW on this pin while RESET
is LOW enables ETM pins (P2[9:0]) to operate
as Trace port after reset.
RSTOUT
20 O RSTOUT — This pin is 3.3 V. LOW on this pin indicates LPC2377/78 being in Reset
state.
RESET
24
[7]
I external reset input: A LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor execution to begin at
address 0. TTL with hysteresis, 5 V tolerant.
XTAL1 31
[8][11]
I Input to the oscillator circuit and internal clock generator circuits.
XTAL2 33
[8][11]
O Output from the oscillator amplifier.
RTCX1 23
[8][12]
I Input to the RTC oscillator circuit.
RTCX2 25
[8][12]
O Output from the RTC oscillator circuit.
V
SS
22, 44,
59, 65,
79, 103,
117,119,
139
[13]
I ground: 0 V reference.
V
SSA
15
[14]
I analog ground: 0 V reference. This pin should nominally be the same voltage as
V
SS
, but should be isolated to minimize noise and error.
Table 3. Pin description …continued
Symbol Pin Type Description