Datasheet

Product data sheet Rev. 6.1 — 16 October 2013 16 of 69

NXP Semiconductors

LPC2377/78

Single-chip 16-bit/32-bit microcontrollers

7. Functional description

7.1 Architectural overview

The LPC2377/78 microcontrollers consist of an ARM7TDMI-S CPU with emulation

support, the ARM7 local bus for closely coupled, high-speed access to most on-chip

memory, the AMBA AHB interfacing to high-speed on-chip peripherals and external

memory, and the AMBA APB for connection to other on-chip peripheral functions. The

microcontroller permanently configures the ARM7TDMI-S processor for little endian byte

order.

The LPC2377/78 implement two AHBs in order to allow the Ethernet block to operate

without interference caused by other system activity. The primary AHB, referred to as

AHB1, includes the VIC, GPDMA controller, and EMC.

The second AHB, referred to as AHB2, includes only the Ethernet block and an

associated 16 kB SRAM. In addition, a bus bridge is provided which allows the secondary

AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into

off-chip memory or unused space in memory residing on AHB1.

In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function,

and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2

are the ARM7 and the Ethernet block.

AHB peripherals are allocated a 2 MB range of addresses at the top of the 4 GB ARM

memory space. Each AHB peripheral is allocated a 16 kB address space within the AHB

address space. Lower speed peripheral functions are connected to the APB bus. The

AHB to APB bridge interfaces the APB to the AHB. APB peripherals are also allocated a

2 MB range of addresses, beginning at the 3.5 GB address point. Each APB peripheral is

allocated a 16 kB address space within the APB address space.

The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers

high performance and low-power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and related

decode mechanism are much simpler than the architecture of microprogrammed complex

instruction set computers. This simplicity results in a high instruction throughput and

impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory

restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM set

• A 16-bit Thumb set